From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 13 Apr 2018 14:58:46 +0000 (+0100)
Subject: add alt rvp
X-Git-Tag: convert-csv-opcode-to-binary~5683
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=eb3b0ec23c6cc6d970eaf425bbb79f0213388940;p=libreriscv.git

add alt rvp
---

diff --git a/alt_rvp.mdwn b/alt_rvp.mdwn
new file mode 100644
index 000000000..2f4b6063c
--- /dev/null
+++ b/alt_rvp.mdwn
@@ -0,0 +1,21 @@
+# Lanes
+
+Example parallel add:
+
+    /* XLEN and N are "baked-in" to the hardware */
+    parameter XLEN;
+    parameter N;
+    /* note that N cannot be greater than XLEN */
+
+    register plane[XLEN];
+    register x[N][32][XLEN];
+
+    function op_add(rd, rs1, rs2) {
+       /* note that this is ADD, not PADD */
+       int i;
+       for (i = 0; i<N; i++)
+          if (plane[i])
+             x[i][rd] <= x[i][rs1] + x[i][rs2];
+    }
+    /* note that "<=" is the Verilog non-blocking assignment operator */
+
diff --git a/simple_v_extension.mdwn b/simple_v_extension.mdwn
index 761fdc4c6..c41191bc3 100644
--- a/simple_v_extension.mdwn
+++ b/simple_v_extension.mdwn
@@ -459,6 +459,31 @@ instructions to deal with corner-cases is thus avoided, and implementors
 get to choose precisely where to focus and target the benefits of their
 implementation efforts, without "extra baggage".
 
+# Example of vector / vector, vector / scalar, scalar / scalar => vector add
+
+    register CSRvectorlen[XLEN][4]; # not quite decided yet about this one...
+    register CSRpredicate[XLEN][4]; # 2^4 is max vector length
+    register CSRreg_is_vectorised[XLEN]; # just for fun support scalars as well
+    register x[32][XLEN];
+
+    function op_add(rd, rs1, rs2, predr)
+    {
+       /* note that this is ADD, not PADD */
+       int i, id, irs1, irs2;
+       # checks CSRvectorlen[rd] == CSRvectorlen[rs] etc. ignored
+       # also destination makes no sense as a scalar but what the hell...
+       for (i = 0, id=0, irs1=0, irs2=0; i<CSRvectorlen[rd]; i++)
+          if (CSRpredicate[predr][i]) # i *think* this is right...
+             x[rd+id] <= x[rs1+irs1] + x[rs2+irs2];
+          # now increment the idxs
+          if (CSRreg_is_vectorised[rd]) # bitfield check rd, scalar/vector?
+             id += 1;
+          if (CSRreg_is_vectorised[rs1]) # bitfield check rs1, scalar/vector?
+             irs1 += 1;
+          if (CSRreg_is_vectorised[rs2]) # bitfield check rs2, scalar/vector?
+             irs2 += 1;
+    }
+
 # V-Extension to Simple-V Comparative Analysis
 
 This section covers the ways in which Simple-V is comparable