From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 23 Sep 2018 08:32:54 +0000 (+0200)
Subject: Added support for ommited "parameter" in Verilog-2001 style parameter decl in SV... 
X-Git-Tag: yosys-0.9~466
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=eb452ffb2861ceac572a4bef6dddb8db3b79deb7;p=yosys.git

Added support for ommited "parameter" in Verilog-2001 style parameter decl in SV mode

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 2389d7d31..63cf646e9 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -881,9 +881,15 @@ param_decl_list:
 
 single_param_decl:
 	TOK_ID '=' expr {
-		if (astbuf1 == nullptr)
-			frontend_verilog_yyerror("syntax error");
-		AstNode *node = astbuf1->clone();
+		AstNode *node;
+		if (astbuf1 == nullptr) {
+			if (!sv_mode)
+				frontend_verilog_yyerror("syntax error");
+			node = new AstNode(AST_PARAMETER);
+			node->children.push_back(AstNode::mkconst_int(0, true));
+		} else {
+			node = astbuf1->clone();
+		}
 		node->str = *$1;
 		delete node->children[0];
 		node->children[0] = $3;