From: colepoirier <colepoirier@gmail.com>
Date: Sun, 7 Jun 2020 00:30:46 +0000 (-0700)
Subject: Fix missing 'comb +='
X-Git-Tag: div_pipeline~519
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=eb481f7545e542550d51c6855a08c7918942d3e1;p=soc.git

Fix missing 'comb +='
---

diff --git a/src/soc/fu/trap/main_stage.py b/src/soc/fu/trap/main_stage.py
index c45e1af2..0bff662c 100644
--- a/src/soc/fu/trap/main_stage.py
+++ b/src/soc/fu/trap/main_stage.py
@@ -159,9 +159,9 @@ class TrapMainStage(PipeModBase):
                     for stt, end in [(1,12), (13, 60), (61, 64)]:
                         comb += msr_o.data[stt:end].eq(a_i[stt:end])
                     with m.If(a_i[MSR_PR]):
-                        msr_o.data[MSR_EE].eq(1)
-                        msr_o.data[MSR_IR].eq(1)
-                        msr_o.data[MSR_DR].eq(1)
+                        comb += msr_o.data[MSR_EE].eq(1)
+                        comb += msr_o.data[MSR_IR].eq(1)
+                        comb += msr_o.data[MSR_DR].eq(1)
                 comb += msr_o.ok.eq(1)
 
             # move from MSR
@@ -180,9 +180,9 @@ class TrapMainStage(PipeModBase):
                 # MSR was in srr1
                 comb += msr_copy(msr_o.data, srr1_i, zero_me=False) # don't zero
                 with m.If(srr1_i[MSR_PR]):
-                        msr_o[MSR_EE].eq(1)
-                        msr_o[MSR_IR].eq(1)
-                        msr_o[MSR_DR].eq(1)
+                        comb += msr_o[MSR_EE].eq(1)
+                        comb += msr_o[MSR_IR].eq(1)
+                        comb += msr_o[MSR_DR].eq(1)
                 comb += msr_o.ok.eq(1)
 
             with m.Case(InternalOp.OP_SC):