From: Gabe Black Date: Sat, 21 Sep 2019 00:42:12 +0000 (-0700) Subject: fastmodel: Templatize the xn versions of the CortexA76. X-Git-Tag: v19.0.0.0~347 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=eb49dec51e8d161aa1430f54981702917d8fad4e;p=gem5.git fastmodel: Templatize the xn versions of the CortexA76. This will make it a lot easier and more succinct to define the x2-x4 versions of that CPU. Change-Id: I951cd3af4419c62892c57968e729fd11c0e4a59e Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21503 Reviewed-by: Giacomo Travaglini Maintainer: Giacomo Travaglini Tested-by: kokoro --- diff --git a/src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py b/src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py new file mode 100644 index 000000000..ebc5b823d --- /dev/null +++ b/src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py @@ -0,0 +1,366 @@ +# Copyright 2019 Google, Inc. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +from m5.params import * +from m5.proxy import * +from m5.SimObject import SimObject + +from m5.objects.ArmInterrupts import ArmInterrupts +from m5.objects.ArmISA import ArmISA +from m5.objects.FastModel import AmbaInitiatorSocket, AmbaTargetSocket +from m5.objects.FastModelArch import FastModelArmCPU +from m5.objects.FastModelGIC import Gicv3CommsTargetSocket +from m5.objects.Gic import ArmPPI +from m5.objects.SystemC import SystemC_ScModule + +class FastModelCortexA76(FastModelArmCPU): + type = 'FastModelCortexA76' + cxx_class = 'FastModel::CortexA76' + cxx_header = 'arch/arm/fastmodel/CortexA76/cortex_a76.hh' + + cntfrq = 0x1800000 + + # We shouldn't need these, but gem5 gets mad without them. + interrupts = [ ArmInterrupts() ] + isa = [ ArmISA() ] + + evs = Parent.evs + + redistributor = Gicv3CommsTargetSocket('GIC communication target') + + CFGEND = Param.Bool(False, "Endianness configuration at reset. "\ + "0, little endian. 1, big endian.") + CFGTE = Param.Bool(False, "Instruction set state when resetting "\ + "into AArch32. 0, A32. 1, T32.") + CRYPTODISABLE = Param.Bool(False, "Disable cryptographic features.") + RVBARADDR = Param.Addr(0x0, "Value of RVBAR_ELx register.") + VINITHI = Param.Bool(False, "Reset value of SCTLR.V.") + enable_trace_special_hlt_imm16 = Param.Bool(False, + "Enable usage of parameter trace_special_hlt_imm16") + l2cache_hit_latency = Param.UInt64(0, "L2 Cache timing annotation "\ + "latency for hit. Intended to model the tag-lookup time. This "\ + "is only used when l2cache-state_modelled=true.") + l2cache_maintenance_latency = Param.UInt64(0, "L2 Cache timing "\ + "annotation latency for cache maintenance operations given in "\ + "total ticks. This is only used when dcache-state_modelled=true.") + l2cache_miss_latency = Param.UInt64(0, "L2 Cache timing annotation "\ + "latency for miss. Intended to model the time for failed "\ + "tag-lookup and allocation of intermediate buffers. This is "\ + "only used when l2cache-state_modelled=true.") + l2cache_read_access_latency = Param.UInt64(0, "L2 Cache timing "\ + "annotation latency for read accesses given in ticks per "\ + "access. If this parameter is non-zero, per-access latencies "\ + "will be used instead of per-byte even if l2cache-read_latency "\ + "is set. This is in addition to the hit or miss latency, and "\ + "intended to correspond to the time taken to transfer across the "\ + "cache upstream bus, this is only used when "\ + "l2cache-state_modelled=true.") + l2cache_read_latency = Param.UInt64(0, "L2 Cache timing annotation "\ + "latency for read accesses given in ticks per byte "\ + "accessed.l2cache-read_access_latency must be set to 0 for "\ + "per-byte latencies to be applied. This is in addition to the "\ + "hit or miss latency, and intended to correspond to the time "\ + "taken to transfer across the cache upstream bus. This is only "\ + "used when l2cache-state_modelled=true.") + l2cache_size = Param.MemorySize32('0x80000', "L2 Cache size in bytes.") + l2cache_snoop_data_transfer_latency = Param.UInt64(0, "L2 Cache "\ + "timing annotation latency for received snoop accesses that "\ + "perform a data transfer given in ticks per byte accessed. This "\ + "is only used when dcache-state_modelled=true.") + l2cache_snoop_issue_latency = Param.UInt64(0, "L2 Cache timing "\ + "annotation latency for snoop accesses issued by this cache in "\ + "total ticks. This is only used when dcache-state_modelled=true.") + l2cache_write_access_latency = Param.UInt64(0, "L2 Cache timing "\ + "annotation latency for write accesses given in ticks per "\ + "access. If this parameter is non-zero, per-access latencies "\ + "will be used instead of per-byte even if l2cache-write_latency "\ + "is set. This is only used when l2cache-state_modelled=true.") + l2cache_write_latency = Param.UInt64(0, "L2 Cache timing annotation "\ + "latency for write accesses given in ticks per byte accessed. "\ + "l2cache-write_access_latency must be set to 0 for per-byte "\ + "latencies to be applied. This is only used when "\ + "l2cache-state_modelled=true.") + max_code_cache_mb = Param.MemorySize32('0x100', "Maximum size of "\ + "the simulation code cache (MiB). For platforms with more than 2 "\ + "cores this limit will be scaled down. (e.g 1/8 for 16 or more "\ + "cores)") + min_sync_level = Param.Unsigned(0, "Force minimum syncLevel "\ + "(0=off=default,1=syncState,2=postInsnIO,3=postInsnAll)") + semihosting_A32_HLT = Param.UInt16(0xf000, + "A32 HLT number for semihosting calls.") + semihosting_A64_HLT = Param.UInt16(0xf000, + "A64 HLT number for semihosting calls.") + semihosting_ARM_SVC = Param.UInt32(0x123456, + "A32 SVC number for semihosting calls.") + semihosting_T32_HLT = Param.Unsigned(60, + "T32 HLT number for semihosting calls.") + semihosting_Thumb_SVC = Param.Unsigned(171, + "T32 SVC number for semihosting calls.") + semihosting_cmd_line = Param.String("", + "Command line available to semihosting calls.") + semihosting_cwd = Param.String("", + "Base directory for semihosting file access.") + semihosting_enable = Param.Bool(True, "Enable semihosting SVC/HLT traps.") + semihosting_heap_base = Param.Addr(0x0, "Virtual address of heap base.") + semihosting_heap_limit = Param.Addr(0xf000000, + "Virtual address of top of heap.") + semihosting_stack_base = Param.Addr(0x10000000, + "Virtual address of base of descending stack.") + semihosting_stack_limit = Param.Addr(0xf000000, + "Virtual address of stack limit.") + trace_special_hlt_imm16 = Param.UInt16(0xf000, "For this HLT "\ + "number, IF enable_trace_special_hlt_imm16=true, skip performing "\ + "usual HLT execution but call MTI trace if registered") + vfp_enable_at_reset = Param.Bool(False, "Enable VFP in CPACR, "\ + "CPPWR, NSACR at reset. Warning: Arm recommends going through "\ + "the implementation's suggested VFP power-up sequence!") + +class FastModelCortexA76Cluster(SimObject): + type = 'FastModelCortexA76Cluster' + cxx_class = 'FastModel::CortexA76Cluster' + cxx_header = 'arch/arm/fastmodel/CortexA76/cortex_a76.hh' + + cores = VectorParam.FastModelCortexA76( + 'Core in a given cluster of CortexA76s') + + evs = Param.SystemC_ScModule( + "Fast mo0del exported virtual subsystem holding cores") + + cnthpirq = Param.ArmInterruptPin(ArmPPI(num=10), + "EL2 physical timer event") + cnthvirq = Param.ArmInterruptPin(ArmPPI(num=12), "EL2 virtual timer event") + cntpsirq = Param.ArmInterruptPin(ArmPPI(num=13), + "EL1 Secure physical timer event") + cntvirq = Param.ArmInterruptPin(ArmPPI(num=11), "Virtual timer event") + commirq = Param.ArmInterruptPin(ArmPPI(num=6), + "Interrupt signal from debug communications channel") + ctidbgirq = Param.ArmInterruptPin(ArmPPI(num=8), + "Cross Trigger Interface (CTI) interrupt trigger output") + pmuirq = Param.ArmInterruptPin(ArmPPI(num=7), + "Interrupt from performance monitoring unit") + vcpumntirq = Param.ArmInterruptPin(ArmPPI(num=9), + "Interrupt signal for virtual CPU maintenance IRQ") + cntpnsirq = Param.ArmInterruptPin(ArmPPI(num=14), + "Non-secure physical timer event") + + amba = AmbaInitiatorSocket(64, 'AMBA initiator socket') + + # These parameters are described in "Fast Models Reference Manual" section + # 3.4.19, "ARMCortexA7x1CT". + BROADCASTATOMIC = Param.Bool(True, "Enable broadcasting of atomic "\ + "operation. The broadcastatomic signal will override this value "\ + "if used") + BROADCASTCACHEMAINT = Param.Bool(True, "Enable broadcasting of cache "\ + "maintenance operations to downstream caches. The "\ + "broadcastcachemaint signal will override this value if used.") + BROADCASTOUTER = Param.Bool(True, "Enable broadcasting of Outer "\ + "Shareable transactions. The broadcastouter signal will override "\ + "this value if used.") + BROADCASTPERSIST = Param.Bool(True, "Enable broadcasting of cache clean "\ + "to the point of persistence operations. The broadcastpersist "\ + "signal will override this value if used") + CLUSTER_ID = Param.UInt16(0x0, "Processor cluster ID value") + GICDISABLE = Param.Bool(True, "Disable the new style GICv3 CPU interface "\ + "in each core model. Should be left enabled unless the platform "\ + "contains a GICv3 distributor.") + cpi_div = Param.UInt32(1, + "Divider for calculating CPI (Cycles Per Instruction)") + cpi_mul = Param.UInt32(1, + "Multiplier for calculating CPI (Cycles Per Instruction)") + dcache_hit_latency = Param.UInt64(0, "L1 D-Cache timing annotation "\ + "latency for hit. Intended to model the tag-lookup time. This "\ + "is only used when dcache-state_modelled=true.") + dcache_maintenance_latency = Param.UInt64(0, "L1 D-Cache timing "\ + "annotation latency for cache maintenance operations given in "\ + "total ticks. This is only used when dcache-state_modelled=true.") + dcache_miss_latency = Param.UInt64(0, "L1 D-Cache timing annotation "\ + "latency for miss. Intended to model the time for failed "\ + "tag-lookup and allocation of intermediate buffers. This is "\ + "only used when dcache-state_modelled=true.") + dcache_prefetch_enabled = Param.Bool(False, "Enable simulation of data "\ + "cache prefetching. This is only used when "\ + "dcache-state_modelled=true") + dcache_read_access_latency = Param.UInt64(0, "L1 D-Cache timing "\ + "annotation latency for read accesses given in ticks per access "\ + "(of size dcache-read_bus_width_in_bytes). If this parameter is "\ + "non-zero, per-access latencies will be used instead of per-byte "\ + "even if dcache-read_latency is set. This is in addition to the "\ + "hit or miss latency, and intended to correspond to the time "\ + "taken to transfer across the cache upstream bus, this is only "\ + "used when dcache-state_modelled=true.") + dcache_read_latency = Param.UInt64(0, "L1 D-Cache timing annotation "\ + "latency for read accesses given in ticks per byte "\ + "accessed.dcache-read_access_latency must be set to 0 for "\ + "per-byte latencies to be applied. This is in addition to the "\ + "hit or miss latency, and intended to correspond to the time "\ + "taken to transfer across the cache upstream bus. This is only "\ + "used when dcache-state_modelled=true.") + dcache_snoop_data_transfer_latency = Param.UInt64(0, "L1 D-Cache timing "\ + "annotation latency for received snoop accesses that perform a data "\ + "transfer given in ticks per byte accessed. This is only used when "\ + "dcache-state_modelled=true.") + dcache_state_modelled = Param.Bool(False, + "Set whether D-cache has stateful implementation") + dcache_write_access_latency = Param.UInt64(0, "L1 D-Cache timing "\ + "annotation latency for write accesses given in ticks per access "\ + "(of size dcache-write_bus_width_in_bytes). If this parameter is "\ + "non-zero, per-access latencies will be used instead of per-byte "\ + "even if dcache-write_latency is set. This is only used when "\ + "dcache-state_modelled=true.") + dcache_write_latency = Param.UInt64(0, "L1 D-Cache timing annotation "\ + "latency for write accesses given in ticks per byte accessed. "\ + "dcache-write_access_latency must be set to 0 for per-byte latencies "\ + "to be applied. This is only used when dcache-state_modelled=true.") + default_opmode = Param.Unsigned(4, "Operating mode of DynamIQ coming out "\ + "of reset. 0: SFONLY ON, 1: 1/4 CACHE ON, 2: 1/2 CACHE ON, 3: "\ + "3/4 CACHE ON, 4: FULL CACHE ON") + diagnostics = Param.Bool(False, "Enable DynamIQ diagnostic messages") + enable_simulation_performance_optimizations = Param.Bool(True, + "With this option enabled, the model will run more quickly, but "\ + "be less accurate to exact CPU behavior. The model will still be "\ + "functionally accurate for software, but may increase "\ + "differences seen between hardware behavior and model behavior "\ + "for certain workloads (it changes the micro-architectural value "\ + "of stage12_tlb_size parameter to 1024).") + ext_abort_device_read_is_sync = Param.Bool(False, + "Synchronous reporting of device-nGnRE read external aborts") + ext_abort_device_write_is_sync = Param.Bool(False, + "Synchronous reporting of device-nGnRE write external aborts") + ext_abort_so_read_is_sync = Param.Bool(False, + "Synchronous reporting of device-nGnRnE read external aborts") + ext_abort_so_write_is_sync = Param.Bool(False, + "Synchronous reporting of device-nGnRnE write external aborts") + gicv3_cpuintf_mmap_access_level = Param.Unsigned(0, "Allowed values are: "\ + "0-mmap access is supported for GICC,GICH,GICV registers. 1-mmap "\ + "access is supported only for GICV registers. 2-mmap access is "\ + "not supported.") + has_peripheral_port = Param.Bool(False, + "If true, additional AXI peripheral port is configured.") + has_statistical_profiling = Param.Bool(True, + "Whether Statistical Based Profiling is implemented") + icache_hit_latency = Param.UInt64(0, "L1 I-Cache timing annotation "\ + "latency for hit. Intended to model the tag-lookup time. This "\ + "is only used when icache-state_modelled=true.") + icache_maintenance_latency = Param.UInt64(0, "L1 I-Cache timing "\ + "annotation latency for cache maintenance operations given in "\ + "total ticks. This is only used when icache-state_modelled=true.") + icache_miss_latency = Param.UInt64(0, "L1 I-Cache timing annotation "\ + "latency for miss. Intended to model the time for failed "\ + "tag-lookup and allocation of intermediate buffers. This is "\ + "only used when icache-state_modelled=true.") + icache_prefetch_enabled = Param.Bool(False, "Enable simulation of "\ + "instruction cache prefetching. This is only used when "\ + "icache-state_modelled=true.") + icache_read_access_latency = Param.UInt64(0, "L1 I-Cache timing "\ + "annotation latency for read accesses given in ticks per access "\ + "(of size icache-read_bus_width_in_bytes). If this parameter is "\ + "non-zero, per-access latencies will be used instead of per-byte "\ + "even if icache-read_latency is set. This is in addition to the "\ + "hit or miss latency, and intended to correspond to the time "\ + "taken to transfer across the cache upstream bus, this is only "\ + "used when icache-state_modelled=true.") + icache_read_latency = Param.UInt64(0, "L1 I-Cache timing annotation "\ + "latency for read accesses given in ticks per byte "\ + "accessed.icache-read_access_latency must be set to 0 for "\ + "per-byte latencies to be applied. This is in addition to the "\ + "hit or miss latency, and intended to correspond to the time "\ + "taken to transfer across the cache upstream bus. This is only "\ + "used when icache-state_modelled=true.") + icache_state_modelled = Param.Bool(False, + "Set whether I-cache has stateful implementation") + l3cache_hit_latency = Param.UInt64(0, "L3 Cache timing annotation "\ + "latency for hit. Intended to model the tag-lookup time. This "\ + "is only used when l3cache-state_modelled=true.") + l3cache_maintenance_latency = Param.UInt64(0, "L3 Cache timing "\ + "annotation latency for cache maintenance operations given in "\ + "total ticks. This is only used when dcache-state_modelled=true.") + l3cache_miss_latency = Param.UInt64(0, "L3 Cache timing annotation "\ + "latency for miss. Intended to model the time for failed "\ + "tag-lookup and allocation of intermediate buffers. This is "\ + "only used when l3cache-state_modelled=true.") + l3cache_read_access_latency = Param.UInt64(0, "L3 Cache timing "\ + "annotation latency for read accesses given in ticks per access "\ + "(of size l3cache-read_bus_width_in_bytes). If this parameter "\ + "is non-zero, per-access latencies will be used instead of "\ + "per-byte even if l3cache-read_latency is set. This is in "\ + "addition to the hit or miss latency, and intended to correspond "\ + "to the time taken to transfer across the cache upstream bus, "\ + "this is only used when l3cache-state_modelled=true.") + l3cache_read_latency = Param.UInt64(0, "L3 Cache timing annotation "\ + "latency for read accesses given in ticks per byte "\ + "accessed.l3cache-read_access_latency must be set to 0 for "\ + "per-byte latencies to be applied. This is in addition to the "\ + "hit or miss latency, and intended to correspond to the time "\ + "taken to transfer across the cache upstream bus. This is only "\ + "used when l3cache-state_modelled=true.") + l3cache_size = Param.MemorySize('0x100000', "L3 Cache size in bytes.") + l3cache_snoop_data_transfer_latency = Param.UInt64(0, "L3 Cache timing "\ + "annotation latency for received snoop accesses that perform a "\ + "data transfer given in ticks per byte accessed. This is only "\ + "used when dcache-state_modelled=true.") + l3cache_snoop_issue_latency = Param.UInt64(0, "L3 Cache timing "\ + "annotation latency for snoop accesses issued by this cache in "\ + "total ticks. This is only used when dcache-state_modelled=true.") + l3cache_write_access_latency = Param.UInt64(0, "L3 Cache timing "\ + "annotation latency for write accesses given in ticks per access "\ + "(of size l3cache-write_bus_width_in_bytes). If this parameter "\ + "is non-zero, per-access latencies will be used instead of "\ + "per-byte even if l3cache-write_latency is set. This is only "\ + "used when l3cache-state_modelled=true.") + l3cache_write_latency = Param.UInt64(0, "L3 Cache timing annotation "\ + "latency for write accesses given in ticks per byte accessed. "\ + "l3cache-write_access_latency must be set to 0 for per-byte "\ + "latencies to be applied. This is only used when "\ + "l3cache-state_modelled=true.") + pchannel_treat_simreset_as_poreset = Param.Bool(False, + "Register core as ON state to cluster with simulation reset.") + periph_address_end = Param.Addr(0x0, "End address for peripheral port "\ + "address range exclusive(corresponds to AENDMP input signal).") + periph_address_start = Param.Addr(0x0, "Start address for peripheral "\ + "port address range inclusive(corresponds to ASTARTMP input "\ + "signal).") + ptw_latency = Param.UInt64(0, "Page table walker latency for TA "\ + "(Timing Annotation), expressed in simulation ticks") + tlb_latency = Param.UInt64(0, "TLB latency for TA (Timing Annotation), "\ + "expressed in simulation ticks") + treat_dcache_cmos_to_pou_as_nop = Param.Bool(False, "Whether dcache "\ + "invalidation to the point of unification is required for "\ + "instruction to data coherence. true - Invalidate operations not "\ + "required") + walk_cache_latency = Param.UInt64(0, "Walk cache latency for TA (Timing "\ + "Annotation), expressed in simulation ticks") + +class FastModelScxEvsCortexA76x1(SystemC_ScModule): + type = 'FastModelScxEvsCortexA76x1' + cxx_class = 'FastModel::ScxEvsCortexA76' + cxx_template_params = [ 'class Types' ] + cxx_header = 'arch/arm/fastmodel/CortexA76/evs.hh' + +class FastModelCortexA76x1(FastModelCortexA76Cluster): + cores = [ FastModelCortexA76(thread_paths=[ 'core.cpu0' ]) ] + + evs = FastModelScxEvsCortexA76x1() diff --git a/src/arch/arm/fastmodel/CortexA76/SConscript b/src/arch/arm/fastmodel/CortexA76/SConscript new file mode 100644 index 000000000..f719874c4 --- /dev/null +++ b/src/arch/arm/fastmodel/CortexA76/SConscript @@ -0,0 +1,42 @@ +# Copyright 2019 Google, Inc. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +Import('*') + +if not env['USE_ARM_FASTMODEL'] or env['TARGET_ISA'] != 'arm': + Return() + +protocol_dir = Dir('..').Dir('protocol') + +ArmFastModelComponent(File('x1.sgproj'), + File('x1.lisa'), + protocol_dir.File( + 'ExportedClockRateControlProtocol.lisa') + ).prepare_env(env) +SimObject('FastModelCortexA76.py') +Source('cortex_a76.cc') +Source('evs.cc') diff --git a/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc b/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc new file mode 100644 index 000000000..0b50f30e4 --- /dev/null +++ b/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc @@ -0,0 +1,212 @@ +/* + * Copyright 2019 Google, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Gabe Black + */ + +#include "arch/arm/fastmodel/CortexA76/cortex_a76.hh" + +#include "arch/arm/fastmodel/arm/cpu.hh" +#include "arch/arm/fastmodel/iris/cpu.hh" +#include "base/logging.hh" +#include "dev/arm/base_gic.hh" +#include "sim/core.hh" +#include "systemc/tlm_bridge/gem5_to_tlm.hh" + +namespace FastModel +{ + +void +CortexA76::setCluster(CortexA76Cluster *_cluster, int _num) +{ + cluster = _cluster; + num = _num; + + set_evs_param("CFGEND", params().CFGEND); + set_evs_param("CFGTE", params().CFGTE); + set_evs_param("CRYPTODISABLE", params().CRYPTODISABLE); + set_evs_param("RVBARADDR", params().RVBARADDR); + set_evs_param("VINITHI", params().VINITHI); + set_evs_param("enable_trace_special_hlt_imm16", + params().enable_trace_special_hlt_imm16); + set_evs_param("l2cache-hit_latency", params().l2cache_hit_latency); + set_evs_param("l2cache-maintenance_latency", + params().l2cache_maintenance_latency); + set_evs_param("l2cache-miss_latency", params().l2cache_miss_latency); + set_evs_param("l2cache-read_access_latency", + params().l2cache_read_access_latency); + set_evs_param("l2cache-read_latency", params().l2cache_read_latency); + set_evs_param("l2cache-size", params().l2cache_size); + set_evs_param("l2cache-snoop_data_transfer_latency", + params().l2cache_snoop_data_transfer_latency); + set_evs_param("l2cache-snoop_issue_latency", + params().l2cache_snoop_issue_latency); + set_evs_param("l2cache-write_access_latency", + params().l2cache_write_access_latency); + set_evs_param("l2cache-write_latency", params().l2cache_write_latency); + set_evs_param("max_code_cache_mb", params().max_code_cache_mb); + set_evs_param("min_sync_level", params().min_sync_level); + set_evs_param("semihosting-A32_HLT", params().semihosting_A32_HLT); + set_evs_param("semihosting-A64_HLT", params().semihosting_A64_HLT); + set_evs_param("semihosting-ARM_SVC", params().semihosting_ARM_SVC); + set_evs_param("semihosting-T32_HLT", params().semihosting_T32_HLT); + set_evs_param("semihosting-Thumb_SVC", params().semihosting_Thumb_SVC); + set_evs_param("semihosting-cmd_line", params().semihosting_cmd_line); + set_evs_param("semihosting-cwd", params().semihosting_cwd); + set_evs_param("semihosting-enable", params().semihosting_enable); + set_evs_param("semihosting-heap_base", params().semihosting_heap_base); + set_evs_param("semihosting-heap_limit", params().semihosting_heap_limit); + set_evs_param("semihosting-stack_base", params().semihosting_stack_base); + set_evs_param("semihosting-stack_limit", params().semihosting_stack_limit); + set_evs_param("trace_special_hlt_imm16", params().trace_special_hlt_imm16); + set_evs_param("vfp-enable_at_reset", params().vfp_enable_at_reset); +} + +Port & +CortexA76::getPort(const std::string &if_name, PortID idx) +{ + if (if_name == "redistributor") + return cluster->getEvs()->gem5_getPort(if_name, num); + else + return ArmCPU::getPort(if_name, idx); +} + +CortexA76Cluster::CortexA76Cluster(Params &p) : + SimObject(&p), _params(p), cores(p.cores), evs(p.evs) +{ + for (int i = 0; i < p.cores.size(); i++) + p.cores[i]->setCluster(this, i); + + sc_core::sc_attr_base *base; + + base = evs->get_attribute(Iris::Gem5CpuClusterAttributeName); + auto *gem5_cluster_attr = + dynamic_cast *>(base); + panic_if(base && !gem5_cluster_attr, + "The EVS gem5 CPU cluster attribute was not of type " + "sc_attribute."); + if (gem5_cluster_attr) + gem5_cluster_attr->value = this; + + set_evs_param("core.BROADCASTATOMIC", p.BROADCASTATOMIC); + set_evs_param("core.BROADCASTCACHEMAINT", p.BROADCASTCACHEMAINT); + set_evs_param("core.BROADCASTOUTER", p.BROADCASTOUTER); + set_evs_param("core.BROADCASTPERSIST", p.BROADCASTPERSIST); + set_evs_param("core.CLUSTER_ID", p.CLUSTER_ID); + set_evs_param("core.GICDISABLE", p.GICDISABLE); + set_evs_param("core.cpi_div", p.cpi_div); + set_evs_param("core.cpi_mul", p.cpi_mul); + set_evs_param("core.dcache-hit_latency", p.dcache_hit_latency); + set_evs_param("core.dcache-maintenance_latency", + p.dcache_maintenance_latency); + set_evs_param("core.dcache-miss_latency", p.dcache_miss_latency); + set_evs_param("core.dcache-prefetch_enabled", + p.dcache_prefetch_enabled); + set_evs_param("core.dcache-read_access_latency", + p.dcache_read_access_latency); + set_evs_param("core.dcache-read_latency", p.dcache_read_latency); + set_evs_param("core.dcache-snoop_data_transfer_latency", + p.dcache_snoop_data_transfer_latency); + set_evs_param("core.dcache-state_modelled", p.dcache_state_modelled); + set_evs_param("core.dcache-write_access_latency", + p.dcache_write_access_latency); + set_evs_param("core.dcache-write_latency", p.dcache_write_latency); + set_evs_param("core.default_opmode", p.default_opmode); + set_evs_param("core.diagnostics", p.diagnostics); + set_evs_param("core.enable_simulation_performance_optimizations", + p.enable_simulation_performance_optimizations); + set_evs_param("core.ext_abort_device_read_is_sync", + p.ext_abort_device_read_is_sync); + set_evs_param("core.ext_abort_device_write_is_sync", + p.ext_abort_device_write_is_sync); + set_evs_param("core.ext_abort_so_read_is_sync", + p.ext_abort_so_read_is_sync); + set_evs_param("core.ext_abort_so_write_is_sync", + p.ext_abort_so_write_is_sync); + set_evs_param("core.gicv3.cpuintf-mmap-access-level", + p.gicv3_cpuintf_mmap_access_level); + set_evs_param("core.has_peripheral_port", p.has_peripheral_port); + set_evs_param("core.has_statistical_profiling", + p.has_statistical_profiling); + set_evs_param("core.icache-hit_latency", p.icache_hit_latency); + set_evs_param("core.icache-maintenance_latency", + p.icache_maintenance_latency); + set_evs_param("core.icache-miss_latency", p.icache_miss_latency); + set_evs_param("core.icache-prefetch_enabled", + p.icache_prefetch_enabled); + set_evs_param("core.icache-read_access_latency", + p.icache_read_access_latency); + set_evs_param("core.icache-read_latency", p.icache_read_latency); + set_evs_param("core.icache-state_modelled", p.icache_state_modelled); + set_evs_param("core.l3cache-hit_latency", p.l3cache_hit_latency); + set_evs_param("core.l3cache-maintenance_latency", + p.l3cache_maintenance_latency); + set_evs_param("core.l3cache-miss_latency", p.l3cache_miss_latency); + set_evs_param("core.l3cache-read_access_latency", + p.l3cache_read_access_latency); + set_evs_param("core.l3cache-read_latency", p.l3cache_read_latency); + set_evs_param("core.l3cache-size", p.l3cache_size); + set_evs_param("core.l3cache-snoop_data_transfer_latency", + p.l3cache_snoop_data_transfer_latency); + set_evs_param("core.l3cache-snoop_issue_latency", + p.l3cache_snoop_issue_latency); + set_evs_param("core.l3cache-write_access_latency", + p.l3cache_write_access_latency); + set_evs_param("core.l3cache-write_latency", p.l3cache_write_latency); + set_evs_param("core.pchannel_treat_simreset_as_poreset", + p.pchannel_treat_simreset_as_poreset); + set_evs_param("core.periph_address_end", p.periph_address_end); + set_evs_param("core.periph_address_start", p.periph_address_start); + set_evs_param("core.ptw_latency", p.ptw_latency); + set_evs_param("core.tlb_latency", p.tlb_latency); + set_evs_param("core.treat-dcache-cmos-to-pou-as-nop", + p.treat_dcache_cmos_to_pou_as_nop); + set_evs_param("core.walk_cache_latency", p.walk_cache_latency); +} + +Port & +CortexA76Cluster::getPort(const std::string &if_name, PortID idx) +{ + if (if_name == "amba") { + return evs->gem5_getPort(if_name, idx); + } else { + return SimObject::getPort(if_name, idx); + } +} + +} // namespace FastModel + +FastModel::CortexA76 * +FastModelCortexA76Params::create() +{ + return new FastModel::CortexA76(*this); +} + +FastModel::CortexA76Cluster * +FastModelCortexA76ClusterParams::create() +{ + return new FastModel::CortexA76Cluster(*this); +} diff --git a/src/arch/arm/fastmodel/CortexA76/cortex_a76.hh b/src/arch/arm/fastmodel/CortexA76/cortex_a76.hh new file mode 100644 index 000000000..c003c7944 --- /dev/null +++ b/src/arch/arm/fastmodel/CortexA76/cortex_a76.hh @@ -0,0 +1,113 @@ +/* + * Copyright 2019 Google, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Gabe Black + */ + +#ifndef __ARCH_ARM_FASTMODEL_CORTEXA76_CORETEX_A76_HH__ +#define __ARCH_ARM_FASTMODEL_CORTEXA76_CORETEX_A76_HH__ + +#include "arch/arm/fastmodel/amba_ports.hh" +#include "arch/arm/fastmodel/arm/cpu.hh" +#include "params/FastModelCortexA76.hh" +#include "params/FastModelCortexA76Cluster.hh" +#include "scx/scx.h" +#include "sim/port.hh" +#include "systemc/ext/core/sc_module.hh" + +class BaseCPU; + +namespace FastModel +{ + +// The fast model exports a class called scx_evs_CortexA76x1 which represents +// the subsystem described in LISA+. This class specializes it to export gem5 +// ports and interface with its peer gem5 CPU. The gem5 CPU inherits from the +// gem5 BaseCPU class and implements its API, while this class actually does +// the work. +class CortexA76Cluster; + +class CortexA76 : public ArmCPU +{ + protected: + typedef FastModelCortexA76Params Params; + const Params &_params; + + CortexA76Cluster *cluster = nullptr; + int num = 0; + + const Params ¶ms() { return _params; } + + public: + CortexA76(Params &p) : ArmCPU(&p), _params(p) {} + + template + void set_evs_param(const std::string &n, T val); + + void setCluster(CortexA76Cluster *_cluster, int _num); + + Port &getPort(const std::string &if_name, + PortID idx=InvalidPortID) override; +}; + +class CortexA76Cluster : public SimObject +{ + private: + typedef FastModelCortexA76ClusterParams Params; + const Params &_params; + + std::vector cores; + sc_core::sc_module *evs; + + public: + template + void + set_evs_param(const std::string &n, T val) + { + scx::scx_set_parameter(evs->name() + std::string(".") + n, val); + } + + CortexA76 *getCore(int num) { return cores.at(num); } + sc_core::sc_module *getEvs() { return evs; } + + CortexA76Cluster(Params &p); + const Params ¶ms() { return _params; } + + Port &getPort(const std::string &if_name, + PortID idx=InvalidPortID) override; +}; + +template +inline void +CortexA76::set_evs_param(const std::string &n, T val) +{ + for (auto &path: params().thread_paths) + cluster->set_evs_param(path + "." + n, val); +} + +} // namespace FastModel + +#endif // __ARCH_ARM_FASTMODEL_CORTEXA76_CORETEX_A76_HH__ diff --git a/src/arch/arm/fastmodel/CortexA76/evs.cc b/src/arch/arm/fastmodel/CortexA76/evs.cc new file mode 100644 index 000000000..263c100ca --- /dev/null +++ b/src/arch/arm/fastmodel/CortexA76/evs.cc @@ -0,0 +1,160 @@ +/* + * Copyright 2019 Google, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Gabe Black + */ + +#include "arch/arm/fastmodel/CortexA76/evs.hh" + +#include "arch/arm/fastmodel/CortexA76/cortex_a76.hh" +#include "arch/arm/fastmodel/arm/cpu.hh" +#include "base/logging.hh" +#include "dev/arm/base_gic.hh" +#include "sim/core.hh" +#include "systemc/tlm_bridge/gem5_to_tlm.hh" + +namespace FastModel +{ + +template +void +ScxEvsCortexA76::clockChangeHandler() +{ + clockRateControl->set_mul_div(SimClock::Int::s, clockPeriod.value); +} + +template +ScxEvsCortexA76::ScxEvsCortexA76( + const sc_core::sc_module_name &mod_name, const Params &p) : + Base(mod_name), amba(Base::amba, p.name + ".amba", -1), + clockChanged(Iris::ClockEventName.c_str()), + clockPeriod(Iris::PeriodAttributeName.c_str()), + gem5CpuCluster(Iris::Gem5CpuClusterAttributeName.c_str()), + sendFunctional(Iris::SendFunctionalAttributeName.c_str()), + params(p) +{ + for (int i = 0; i < CoreCount; i++) { + redist.emplace_back(new TlmGicTarget(this->redistributor[i], + csprintf("%s.redistributor[%d]", name(), i), i)); + cnthpirq.emplace_back(new SignalReceiver(csprintf("cnthpirq[%d]", i))); + cnthvirq.emplace_back(new SignalReceiver(csprintf("cnthvirq[%d]", i))); + cntpsirq.emplace_back(new SignalReceiver(csprintf("cntpsirq[%d]", i))); + cntvirq.emplace_back(new SignalReceiver(csprintf("cntvirq[%d]", i))); + commirq.emplace_back(new SignalReceiver(csprintf("commirq[%d]", i))); + ctidbgirq.emplace_back( + new SignalReceiver(csprintf("ctidbgirq[%d]", i))); + pmuirq.emplace_back(new SignalReceiver(csprintf("pmuirq[%d]", i))); + vcpumntirq.emplace_back( + new SignalReceiver(csprintf("vcpumntirq[%d]", i))); + cntpnsirq.emplace_back( + new SignalReceiver(csprintf("cntpnsirq[%d]", i))); + + Base::cnthpirq[i].bind(cnthpirq[i]->signal_in); + Base::cnthvirq[i].bind(cnthvirq[i]->signal_in); + Base::cntpsirq[i].bind(cntpsirq[i]->signal_in); + Base::cntvirq[i].bind(cntvirq[i]->signal_in); + Base::commirq[i].bind(commirq[i]->signal_in); + Base::ctidbgirq[i].bind(ctidbgirq[i]->signal_in); + Base::pmuirq[i].bind(pmuirq[i]->signal_in); + Base::vcpumntirq[i].bind(vcpumntirq[i]->signal_in); + Base::cntpnsirq[i].bind(cntpnsirq[i]->signal_in); + } + + clockRateControl.bind(this->clock_rate_s); + + this->add_attribute(gem5CpuCluster); + this->add_attribute(clockPeriod); + SC_METHOD(clockChangeHandler); + this->dont_initialize(); + this->sensitive << clockChanged; + + sendFunctional.value = [this](PacketPtr pkt) { sendFunc(pkt); }; + this->add_attribute(sendFunctional); +} + +template +void +ScxEvsCortexA76::sendFunc(PacketPtr pkt) +{ + auto *trans = sc_gem5::packet2payload(pkt); + panic_if(Base::amba->transport_dbg(*trans) != trans->get_data_length(), + "Didn't send entire functional packet!"); + trans->release(); +} + +template +void +ScxEvsCortexA76::before_end_of_elaboration() +{ + Base::before_end_of_elaboration(); + + auto *cluster = gem5CpuCluster.value; + + auto set_on_change = [cluster]( + SignalReceiver &recv, ArmInterruptPinGen *gen, int num) + { + auto *pin = gen->get(cluster->getCore(num)->getContext(0)); + auto handler = [pin](bool status) + { + status ? pin->raise() : pin->clear(); + }; + recv.onChange(handler); + }; + + for (int i = 0; i < CoreCount; i++) { + set_on_change(*cnthpirq[i], cluster->params().cnthpirq, i); + set_on_change(*cnthvirq[i], cluster->params().cnthvirq, i); + set_on_change(*cntpsirq[i], cluster->params().cntpsirq, i); + set_on_change(*cntvirq[i], cluster->params().cntvirq, i); + set_on_change(*commirq[i], cluster->params().commirq, i); + set_on_change(*ctidbgirq[i], cluster->params().ctidbgirq, i); + set_on_change(*pmuirq[i], cluster->params().pmuirq, i); + set_on_change(*vcpumntirq[i], cluster->params().vcpumntirq, i); + set_on_change(*cntpnsirq[i], cluster->params().cntpnsirq, i); + } +} + +template +Port & +ScxEvsCortexA76::gem5_getPort(const std::string &if_name, int idx) +{ + if (if_name == "redistributor") + return *redist.at(idx); + else if (if_name == "amba") + return amba; + else + return Base::gem5_getPort(if_name, idx); +} + +template class ScxEvsCortexA76; + +} // namespace FastModel + +FastModel::ScxEvsCortexA76x1 * +FastModelScxEvsCortexA76x1Params::create() +{ + return new FastModel::ScxEvsCortexA76x1(name.c_str(), *this); +} diff --git a/src/arch/arm/fastmodel/CortexA76/evs.hh b/src/arch/arm/fastmodel/CortexA76/evs.hh new file mode 100644 index 000000000..a9783a3b1 --- /dev/null +++ b/src/arch/arm/fastmodel/CortexA76/evs.hh @@ -0,0 +1,117 @@ +/* + * Copyright 2019 Google, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Gabe Black + */ + +#ifndef __ARCH_ARM_FASTMODEL_CORTEXA76_EVS_HH__ +#define __ARCH_ARM_FASTMODEL_CORTEXA76_EVS_HH__ + +#include + +#include "arch/arm/fastmodel/amba_ports.hh" +#include "arch/arm/fastmodel/common/signal_receiver.hh" +#include "arch/arm/fastmodel/protocol/exported_clock_rate_control.hh" +#include "mem/port_proxy.hh" +#include "params/FastModelScxEvsCortexA76x1.hh" +#include "scx_evs_CortexA76x1.h" +#include "systemc/ext/core/sc_event.hh" +#include "systemc/ext/core/sc_module.hh" +#include "systemc/tlm_port_wrapper.hh" + +namespace FastModel +{ + +class CortexA76Cluster; + +template +class ScxEvsCortexA76 : public Types::Base +{ + private: + static const int CoreCount = Types::CoreCount; + using Base = typename Types::Base; + using Params = typename Types::Params; + + SC_HAS_PROCESS(ScxEvsCortexA76); + + ClockRateControlInitiatorSocket clockRateControl; + + typedef sc_gem5::TlmTargetBaseWrapper< + 64, svp_gicv3_comms::gicv3_comms_fw_if, + svp_gicv3_comms::gicv3_comms_bw_if, 1, + sc_core::SC_ONE_OR_MORE_BOUND> TlmGicTarget; + + AmbaInitiator amba; + std::vector> redist; + + std::vector> cnthpirq; + std::vector> cnthvirq; + std::vector> cntpsirq; + std::vector> cntvirq; + std::vector> commirq; + std::vector> ctidbgirq; + std::vector> pmuirq; + std::vector> vcpumntirq; + std::vector> cntpnsirq; + + sc_core::sc_event clockChanged; + sc_core::sc_attribute clockPeriod; + sc_core::sc_attribute gem5CpuCluster; + sc_core::sc_attribute sendFunctional; + + void sendFunc(PacketPtr pkt); + + void clockChangeHandler(); + + const Params ¶ms; + + public: + ScxEvsCortexA76(const sc_core::sc_module_name &mod_name, const Params &p); + + void before_end_of_elaboration() override; + Port &gem5_getPort(const std::string &if_name, int idx) override; + + void + end_of_elaboration() override + { + Base::end_of_elaboration(); + Base::start_of_simulation(); + } + void start_of_simulation() override {} +}; + +struct ScxEvsCortexA76x1Types +{ + using Base = scx_evs_CortexA76x1; + using Params = FastModelScxEvsCortexA76x1Params; + static const int CoreCount = 1; +}; +using ScxEvsCortexA76x1 = ScxEvsCortexA76; +extern template class ScxEvsCortexA76; + +} // namespace FastModel + +#endif // __ARCH_ARM_FASTMODEL_CORTEXA76_EVS_HH__ diff --git a/src/arch/arm/fastmodel/CortexA76/x1.lisa b/src/arch/arm/fastmodel/CortexA76/x1.lisa new file mode 100644 index 000000000..675521d20 --- /dev/null +++ b/src/arch/arm/fastmodel/CortexA76/x1.lisa @@ -0,0 +1,118 @@ +/* + * Copyright 2019 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Gabe Black + */ + +component CortexA76x1 +{ + + composition + { + core : ARMCortexA76x1CT(); + + // Bridges for the core. + ambaBridge : PVBus2AMBAPV(); + + // Adapters for CPU-to-GIC signals + CNTHPIRQ : SGSignal2AMBAPVSignal(); + CNTHVIRQ : SGSignal2AMBAPVSignal(); + CNTPNSIRQ : SGSignal2AMBAPVSignal(); + CNTPSIRQ : SGSignal2AMBAPVSignal(); + CNTVIRQ : SGSignal2AMBAPVSignal(); + COMMIRQ : SGSignal2AMBAPVSignal(); + CTIDBGIRQ : SGSignal2AMBAPVSignal(); + PMUIRQ : SGSignal2AMBAPVSignal(); + VCPUMNTIRQ : SGSignal2AMBAPVSignal(); + + // Clocks. + clock1Hz : MasterClock(); + clockDiv : ClockDivider(); + clockDivPeriph : ClockDivider(mul=0x01800000); + } + + connection + { + // The main interface with memory. + core.pvbus_m0 => ambaBridge.pvbus_s; + ambaBridge.amba_pv_m => self.amba; + + // Connection to the GIC. + self.redistributor => core.gicv3_redistributor_s; + + // Connections from CPU to adapters + core.CNTHPIRQ[0] => CNTHPIRQ.sg_signal_s; + CNTHPIRQ.amba_pv_signal_m => self.cnthpirq[0]; + core.CNTHVIRQ[0] => CNTHVIRQ.sg_signal_s; + CNTHVIRQ.amba_pv_signal_m => self.cnthvirq[0]; + core.CNTPNSIRQ[0] => CNTPNSIRQ.sg_signal_s; + CNTPNSIRQ.amba_pv_signal_m => self.cntpnsirq[0]; + core.CNTPSIRQ[0] => CNTPSIRQ.sg_signal_s; + CNTPSIRQ.amba_pv_signal_m => self.cntpsirq[0]; + core.CNTVIRQ[0] => CNTVIRQ.sg_signal_s; + CNTVIRQ.amba_pv_signal_m => self.cntvirq[0]; + core.commirq[0] => COMMIRQ.sg_signal_s; + COMMIRQ.amba_pv_signal_m => self.commirq[0]; + core.ctidbgirq[0] => CTIDBGIRQ.sg_signal_s; + CTIDBGIRQ.amba_pv_signal_m => self.ctidbgirq[0]; + core.pmuirq[0] => PMUIRQ.sg_signal_s; + PMUIRQ.amba_pv_signal_m => self.pmuirq[0]; + core.vcpumntirq[0] => VCPUMNTIRQ.sg_signal_s; + VCPUMNTIRQ.amba_pv_signal_m => self.vcpumntirq[0]; + + // Clocks. + clock1Hz.clk_out => clockDiv.clk_in; + clock1Hz.clk_out => clockDivPeriph.clk_in; + clockDiv.clk_out => core.core_clk_in; + clockDivPeriph.clk_out => core.clk_in; + } + + properties + { + component_type = "System"; + } + + master port amba; + slave port clock_rate_s + { + behavior set_mul_div(uint64_t mul, uint64_t div) + { + clockDiv.rate.set64(mul, div); + } + } + slave port redistributor[1]; + + // External ports for CPU-to-GIC signals + master port cnthpirq[1]; + master port cnthvirq[1]; + master port cntpsirq[1]; + master port cntvirq[1]; + master port commirq[1]; + master port ctidbgirq[1]; + master port pmuirq[1]; + master port vcpumntirq[1]; + master port cntpnsirq[1]; +} diff --git a/src/arch/arm/fastmodel/CortexA76/x1.sgproj b/src/arch/arm/fastmodel/CortexA76/x1.sgproj new file mode 100644 index 000000000..4f14dd20f --- /dev/null +++ b/src/arch/arm/fastmodel/CortexA76/x1.sgproj @@ -0,0 +1,28 @@ +sgproject "x1.sgproj" +{ +TOP_LEVEL_COMPONENT = "CortexA76x1"; +ACTIVE_CONFIG_LINUX = "gcc"; +ACTIVE_CONFIG_WINDOWS = "Win64-Release-VC2015"; +config "gcc" +{ + ADDITIONAL_COMPILER_SETTINGS = "-O3 -Wall -std=c++11 -Wno-deprecated -Wno-unused-function"; + ADDITIONAL_LINKER_SETTINGS = "-Wl,--no-undefined"; + BUILD_DIR = "./gcc"; + COMPILER = "gcc-6.4"; + CONFIG_DESCRIPTION = ""; + CONFIG_NAME = "gcc"; + PLATFORM = "Linux64"; + PREPROCESSOR_DEFINES = "NDEBUG"; + SIMGEN_COMMAND_LINE = "--num-comps-file 50"; + TARGET_MAXVIEW = "0"; + TARGET_SYSTEMC = "1"; + + INCLUDE_DIRS="../../../../"; +} +files +{ + path = "x1.lisa"; + path = "${PVLIB_HOME}/etc/sglib.sgrepo"; + path = "../protocol/ExportedClockRateControlProtocol.lisa"; +} +} diff --git a/src/arch/arm/fastmodel/CortexA76x1/CortexA76x1.lisa b/src/arch/arm/fastmodel/CortexA76x1/CortexA76x1.lisa deleted file mode 100644 index feedaaccc..000000000 --- a/src/arch/arm/fastmodel/CortexA76x1/CortexA76x1.lisa +++ /dev/null @@ -1,118 +0,0 @@ -/* - * Copyright 2019 Google Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Gabe Black - */ - -component CortexA76x1 -{ - - composition - { - core : ARMCortexA76x1CT(); - - // Bridges for the core. - ambaBridge : PVBus2AMBAPV(); - - // Adapters for CPU-to-GIC signals - CNTHPIRQ : SGSignal2AMBAPVSignal(); - CNTHVIRQ : SGSignal2AMBAPVSignal(); - CNTPNSIRQ : SGSignal2AMBAPVSignal(); - CNTPSIRQ : SGSignal2AMBAPVSignal(); - CNTVIRQ : SGSignal2AMBAPVSignal(); - COMMIRQ : SGSignal2AMBAPVSignal(); - CTIDBGIRQ : SGSignal2AMBAPVSignal(); - PMUIRQ : SGSignal2AMBAPVSignal(); - VCPUMNTIRQ : SGSignal2AMBAPVSignal(); - - // Clocks. - clock1Hz : MasterClock(); - clockDiv : ClockDivider(); - clockDivPeriph : ClockDivider(mul=0x01800000); - } - - connection - { - // The main interface with memory. - core.pvbus_m0 => ambaBridge.pvbus_s; - ambaBridge.amba_pv_m => self.amba; - - // Connection to the GIC. - self.redistributor => core.gicv3_redistributor_s; - - // Connections from CPU to adapters - core.CNTHPIRQ[0] => CNTHPIRQ.sg_signal_s; - CNTHPIRQ.amba_pv_signal_m => self.cnthpirq[0]; - core.CNTHVIRQ[0] => CNTHVIRQ.sg_signal_s; - CNTHVIRQ.amba_pv_signal_m => self.cnthvirq[0]; - core.CNTPNSIRQ[0] => CNTPNSIRQ.sg_signal_s; - CNTPNSIRQ.amba_pv_signal_m => self.cntpnsirq[0]; - core.CNTPSIRQ[0] => CNTPSIRQ.sg_signal_s; - CNTPSIRQ.amba_pv_signal_m => self.cntpsirq[0]; - core.CNTVIRQ[0] => CNTVIRQ.sg_signal_s; - CNTVIRQ.amba_pv_signal_m => self.cntvirq[0]; - core.commirq[0] => COMMIRQ.sg_signal_s; - COMMIRQ.amba_pv_signal_m => self.commirq[0]; - core.ctidbgirq[0] => CTIDBGIRQ.sg_signal_s; - CTIDBGIRQ.amba_pv_signal_m => self.ctidbgirq[0]; - core.pmuirq[0] => PMUIRQ.sg_signal_s; - PMUIRQ.amba_pv_signal_m => self.pmuirq[0]; - core.vcpumntirq[0] => VCPUMNTIRQ.sg_signal_s; - VCPUMNTIRQ.amba_pv_signal_m => self.vcpumntirq[0]; - - // Clocks. - clock1Hz.clk_out => clockDiv.clk_in; - clock1Hz.clk_out => clockDivPeriph.clk_in; - clockDiv.clk_out => core.core_clk_in[0]; - clockDivPeriph.clk_out => core.clk_in; - } - - properties - { - component_type = "System"; - } - - master port amba; - slave port clock_rate_s - { - behavior set_mul_div(uint64_t mul, uint64_t div) - { - clockDiv.rate.set64(mul, div); - } - } - slave port redistributor[1]; - - // External ports for CPU-to-GIC signals - master port cnthpirq[1]; - master port cnthvirq[1]; - master port cntpsirq[1]; - master port cntvirq[1]; - master port commirq[1]; - master port ctidbgirq[1]; - master port pmuirq[1]; - master port vcpumntirq[1]; - master port cntpnsirq[1]; -} diff --git a/src/arch/arm/fastmodel/CortexA76x1/CortexA76x1.sgproj b/src/arch/arm/fastmodel/CortexA76x1/CortexA76x1.sgproj deleted file mode 100644 index e3912514c..000000000 --- a/src/arch/arm/fastmodel/CortexA76x1/CortexA76x1.sgproj +++ /dev/null @@ -1,28 +0,0 @@ -sgproject "CortexA76x1.sgproj" -{ -TOP_LEVEL_COMPONENT = "CortexA76x1"; -ACTIVE_CONFIG_LINUX = "gcc"; -ACTIVE_CONFIG_WINDOWS = "Win64-Release-VC2015"; -config "gcc" -{ - ADDITIONAL_COMPILER_SETTINGS = "-O3 -Wall -std=c++11 -Wno-deprecated -Wno-unused-function"; - ADDITIONAL_LINKER_SETTINGS = "-Wl,--no-undefined"; - BUILD_DIR = "./gcc"; - COMPILER = "gcc-6.4"; - CONFIG_DESCRIPTION = ""; - CONFIG_NAME = "gcc"; - PLATFORM = "Linux64"; - PREPROCESSOR_DEFINES = "NDEBUG"; - SIMGEN_COMMAND_LINE = "--num-comps-file 50"; - TARGET_MAXVIEW = "0"; - TARGET_SYSTEMC = "1"; - - INCLUDE_DIRS="../../../../"; -} -files -{ - path = "CortexA76x1.lisa"; - path = "${PVLIB_HOME}/etc/sglib.sgrepo"; - path = "../protocol/ExportedClockRateControlProtocol.lisa"; -} -} diff --git a/src/arch/arm/fastmodel/CortexA76x1/FastModelCortexA76x1.py b/src/arch/arm/fastmodel/CortexA76x1/FastModelCortexA76x1.py deleted file mode 100644 index f775f569d..000000000 --- a/src/arch/arm/fastmodel/CortexA76x1/FastModelCortexA76x1.py +++ /dev/null @@ -1,365 +0,0 @@ -# Copyright 2019 Google, Inc. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are -# met: redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer; -# redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution; -# neither the name of the copyright holders nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -# Authors: Gabe Black - -from m5.params import * -from m5.proxy import * -from m5.SimObject import SimObject - -from m5.objects.ArmInterrupts import ArmInterrupts -from m5.objects.ArmISA import ArmISA -from m5.objects.FastModel import AmbaInitiatorSocket, AmbaTargetSocket -from m5.objects.FastModelArch import FastModelArmCPU -from m5.objects.FastModelGIC import Gicv3CommsTargetSocket -from m5.objects.Gic import ArmPPI -from m5.objects.SystemC import SystemC_ScModule - -class FastModelCortexA76(FastModelArmCPU): - type = 'FastModelCortexA76' - cxx_class = 'FastModel::CortexA76' - cxx_header = 'arch/arm/fastmodel/CortexA76x1/cortex_a76x1.hh' - - cntfrq = 0x1800000 - - # We shouldn't need these, but gem5 gets mad without them. - interrupts = [ ArmInterrupts() ] - isa = [ ArmISA() ] - - evs = Parent.evs - - redistributor = Gicv3CommsTargetSocket('GIC communication target') - - CFGEND = Param.Bool(False, "Endianness configuration at reset. "\ - "0, little endian. 1, big endian.") - CFGTE = Param.Bool(False, "Instruction set state when resetting "\ - "into AArch32. 0, A32. 1, T32.") - CRYPTODISABLE = Param.Bool(False, "Disable cryptographic features.") - RVBARADDR = Param.Addr(0x0, "Value of RVBAR_ELx register.") - VINITHI = Param.Bool(False, "Reset value of SCTLR.V.") - enable_trace_special_hlt_imm16 = Param.Bool(False, - "Enable usage of parameter trace_special_hlt_imm16") - l2cache_hit_latency = Param.UInt64(0, "L2 Cache timing annotation "\ - "latency for hit. Intended to model the tag-lookup time. This "\ - "is only used when l2cache-state_modelled=true.") - l2cache_maintenance_latency = Param.UInt64(0, "L2 Cache timing "\ - "annotation latency for cache maintenance operations given in "\ - "total ticks. This is only used when dcache-state_modelled=true.") - l2cache_miss_latency = Param.UInt64(0, "L2 Cache timing annotation "\ - "latency for miss. Intended to model the time for failed "\ - "tag-lookup and allocation of intermediate buffers. This is "\ - "only used when l2cache-state_modelled=true.") - l2cache_read_access_latency = Param.UInt64(0, "L2 Cache timing "\ - "annotation latency for read accesses given in ticks per "\ - "access. If this parameter is non-zero, per-access latencies "\ - "will be used instead of per-byte even if l2cache-read_latency "\ - "is set. This is in addition to the hit or miss latency, and "\ - "intended to correspond to the time taken to transfer across the "\ - "cache upstream bus, this is only used when "\ - "l2cache-state_modelled=true.") - l2cache_read_latency = Param.UInt64(0, "L2 Cache timing annotation "\ - "latency for read accesses given in ticks per byte "\ - "accessed.l2cache-read_access_latency must be set to 0 for "\ - "per-byte latencies to be applied. This is in addition to the "\ - "hit or miss latency, and intended to correspond to the time "\ - "taken to transfer across the cache upstream bus. This is only "\ - "used when l2cache-state_modelled=true.") - l2cache_size = Param.MemorySize32('0x80000', "L2 Cache size in bytes.") - l2cache_snoop_data_transfer_latency = Param.UInt64(0, "L2 Cache "\ - "timing annotation latency for received snoop accesses that "\ - "perform a data transfer given in ticks per byte accessed. This "\ - "is only used when dcache-state_modelled=true.") - l2cache_snoop_issue_latency = Param.UInt64(0, "L2 Cache timing "\ - "annotation latency for snoop accesses issued by this cache in "\ - "total ticks. This is only used when dcache-state_modelled=true.") - l2cache_write_access_latency = Param.UInt64(0, "L2 Cache timing "\ - "annotation latency for write accesses given in ticks per "\ - "access. If this parameter is non-zero, per-access latencies "\ - "will be used instead of per-byte even if l2cache-write_latency "\ - "is set. This is only used when l2cache-state_modelled=true.") - l2cache_write_latency = Param.UInt64(0, "L2 Cache timing annotation "\ - "latency for write accesses given in ticks per byte accessed. "\ - "l2cache-write_access_latency must be set to 0 for per-byte "\ - "latencies to be applied. This is only used when "\ - "l2cache-state_modelled=true.") - max_code_cache_mb = Param.MemorySize32('0x100', "Maximum size of "\ - "the simulation code cache (MiB). For platforms with more than 2 "\ - "cores this limit will be scaled down. (e.g 1/8 for 16 or more "\ - "cores)") - min_sync_level = Param.Unsigned(0, "Force minimum syncLevel "\ - "(0=off=default,1=syncState,2=postInsnIO,3=postInsnAll)") - semihosting_A32_HLT = Param.UInt16(0xf000, - "A32 HLT number for semihosting calls.") - semihosting_A64_HLT = Param.UInt16(0xf000, - "A64 HLT number for semihosting calls.") - semihosting_ARM_SVC = Param.UInt32(0x123456, - "A32 SVC number for semihosting calls.") - semihosting_T32_HLT = Param.Unsigned(60, - "T32 HLT number for semihosting calls.") - semihosting_Thumb_SVC = Param.Unsigned(171, - "T32 SVC number for semihosting calls.") - semihosting_cmd_line = Param.String("", - "Command line available to semihosting calls.") - semihosting_cwd = Param.String("", - "Base directory for semihosting file access.") - semihosting_enable = Param.Bool(True, "Enable semihosting SVC/HLT traps.") - semihosting_heap_base = Param.Addr(0x0, "Virtual address of heap base.") - semihosting_heap_limit = Param.Addr(0xf000000, - "Virtual address of top of heap.") - semihosting_stack_base = Param.Addr(0x10000000, - "Virtual address of base of descending stack.") - semihosting_stack_limit = Param.Addr(0xf000000, - "Virtual address of stack limit.") - trace_special_hlt_imm16 = Param.UInt16(0xf000, "For this HLT "\ - "number, IF enable_trace_special_hlt_imm16=true, skip performing "\ - "usual HLT execution but call MTI trace if registered") - vfp_enable_at_reset = Param.Bool(False, "Enable VFP in CPACR, "\ - "CPPWR, NSACR at reset. Warning: Arm recommends going through "\ - "the implementation's suggested VFP power-up sequence!") - -class FastModelCortexA76Cluster(SimObject): - type = 'FastModelCortexA76Cluster' - cxx_class = 'FastModel::CortexA76Cluster' - cxx_header = 'arch/arm/fastmodel/CortexA76x1/cortex_a76x1.hh' - - cores = VectorParam.FastModelCortexA76( - 'Core in a given cluster of CortexA76s') - - evs = Param.SystemC_ScModule( - "Fast mo0del exported virtual subsystem holding cores") - - cnthpirq = Param.ArmInterruptPin(ArmPPI(num=10), - "EL2 physical timer event") - cnthvirq = Param.ArmInterruptPin(ArmPPI(num=12), "EL2 virtual timer event") - cntpsirq = Param.ArmInterruptPin(ArmPPI(num=13), - "EL1 Secure physical timer event") - cntvirq = Param.ArmInterruptPin(ArmPPI(num=11), "Virtual timer event") - commirq = Param.ArmInterruptPin(ArmPPI(num=6), - "Interrupt signal from debug communications channel") - ctidbgirq = Param.ArmInterruptPin(ArmPPI(num=8), - "Cross Trigger Interface (CTI) interrupt trigger output") - pmuirq = Param.ArmInterruptPin(ArmPPI(num=7), - "Interrupt from performance monitoring unit") - vcpumntirq = Param.ArmInterruptPin(ArmPPI(num=9), - "Interrupt signal for virtual CPU maintenance IRQ") - cntpnsirq = Param.ArmInterruptPin(ArmPPI(num=14), - "Non-secure physical timer event") - - amba = AmbaInitiatorSocket(64, 'AMBA initiator socket') - - # These parameters are described in "Fast Models Reference Manual" section - # 3.4.19, "ARMCortexA7x1CT". - BROADCASTATOMIC = Param.Bool(True, "Enable broadcasting of atomic "\ - "operation. The broadcastatomic signal will override this value "\ - "if used") - BROADCASTCACHEMAINT = Param.Bool(True, "Enable broadcasting of cache "\ - "maintenance operations to downstream caches. The "\ - "broadcastcachemaint signal will override this value if used.") - BROADCASTOUTER = Param.Bool(True, "Enable broadcasting of Outer "\ - "Shareable transactions. The broadcastouter signal will override "\ - "this value if used.") - BROADCASTPERSIST = Param.Bool(True, "Enable broadcasting of cache clean "\ - "to the point of persistence operations. The broadcastpersist "\ - "signal will override this value if used") - CLUSTER_ID = Param.UInt16(0x0, "Processor cluster ID value") - GICDISABLE = Param.Bool(True, "Disable the new style GICv3 CPU interface "\ - "in each core model. Should be left enabled unless the platform "\ - "contains a GICv3 distributor.") - cpi_div = Param.UInt32(1, - "Divider for calculating CPI (Cycles Per Instruction)") - cpi_mul = Param.UInt32(1, - "Multiplier for calculating CPI (Cycles Per Instruction)") - dcache_hit_latency = Param.UInt64(0, "L1 D-Cache timing annotation "\ - "latency for hit. Intended to model the tag-lookup time. This "\ - "is only used when dcache-state_modelled=true.") - dcache_maintenance_latency = Param.UInt64(0, "L1 D-Cache timing "\ - "annotation latency for cache maintenance operations given in "\ - "total ticks. This is only used when dcache-state_modelled=true.") - dcache_miss_latency = Param.UInt64(0, "L1 D-Cache timing annotation "\ - "latency for miss. Intended to model the time for failed "\ - "tag-lookup and allocation of intermediate buffers. This is "\ - "only used when dcache-state_modelled=true.") - dcache_prefetch_enabled = Param.Bool(False, "Enable simulation of data "\ - "cache prefetching. This is only used when "\ - "dcache-state_modelled=true") - dcache_read_access_latency = Param.UInt64(0, "L1 D-Cache timing "\ - "annotation latency for read accesses given in ticks per access "\ - "(of size dcache-read_bus_width_in_bytes). If this parameter is "\ - "non-zero, per-access latencies will be used instead of per-byte "\ - "even if dcache-read_latency is set. This is in addition to the "\ - "hit or miss latency, and intended to correspond to the time "\ - "taken to transfer across the cache upstream bus, this is only "\ - "used when dcache-state_modelled=true.") - dcache_read_latency = Param.UInt64(0, "L1 D-Cache timing annotation "\ - "latency for read accesses given in ticks per byte "\ - "accessed.dcache-read_access_latency must be set to 0 for "\ - "per-byte latencies to be applied. This is in addition to the "\ - "hit or miss latency, and intended to correspond to the time "\ - "taken to transfer across the cache upstream bus. This is only "\ - "used when dcache-state_modelled=true.") - dcache_snoop_data_transfer_latency = Param.UInt64(0, "L1 D-Cache timing "\ - "annotation latency for received snoop accesses that perform a data "\ - "transfer given in ticks per byte accessed. This is only used when "\ - "dcache-state_modelled=true.") - dcache_state_modelled = Param.Bool(False, - "Set whether D-cache has stateful implementation") - dcache_write_access_latency = Param.UInt64(0, "L1 D-Cache timing "\ - "annotation latency for write accesses given in ticks per access "\ - "(of size dcache-write_bus_width_in_bytes). If this parameter is "\ - "non-zero, per-access latencies will be used instead of per-byte "\ - "even if dcache-write_latency is set. This is only used when "\ - "dcache-state_modelled=true.") - dcache_write_latency = Param.UInt64(0, "L1 D-Cache timing annotation "\ - "latency for write accesses given in ticks per byte accessed. "\ - "dcache-write_access_latency must be set to 0 for per-byte latencies "\ - "to be applied. This is only used when dcache-state_modelled=true.") - default_opmode = Param.Unsigned(4, "Operating mode of DynamIQ coming out "\ - "of reset. 0: SFONLY ON, 1: 1/4 CACHE ON, 2: 1/2 CACHE ON, 3: "\ - "3/4 CACHE ON, 4: FULL CACHE ON") - diagnostics = Param.Bool(False, "Enable DynamIQ diagnostic messages") - enable_simulation_performance_optimizations = Param.Bool(True, - "With this option enabled, the model will run more quickly, but "\ - "be less accurate to exact CPU behavior. The model will still be "\ - "functionally accurate for software, but may increase "\ - "differences seen between hardware behavior and model behavior "\ - "for certain workloads (it changes the micro-architectural value "\ - "of stage12_tlb_size parameter to 1024).") - ext_abort_device_read_is_sync = Param.Bool(False, - "Synchronous reporting of device-nGnRE read external aborts") - ext_abort_device_write_is_sync = Param.Bool(False, - "Synchronous reporting of device-nGnRE write external aborts") - ext_abort_so_read_is_sync = Param.Bool(False, - "Synchronous reporting of device-nGnRnE read external aborts") - ext_abort_so_write_is_sync = Param.Bool(False, - "Synchronous reporting of device-nGnRnE write external aborts") - gicv3_cpuintf_mmap_access_level = Param.Unsigned(0, "Allowed values are: "\ - "0-mmap access is supported for GICC,GICH,GICV registers. 1-mmap "\ - "access is supported only for GICV registers. 2-mmap access is "\ - "not supported.") - has_peripheral_port = Param.Bool(False, - "If true, additional AXI peripheral port is configured.") - has_statistical_profiling = Param.Bool(True, - "Whether Statistical Based Profiling is implemented") - icache_hit_latency = Param.UInt64(0, "L1 I-Cache timing annotation "\ - "latency for hit. Intended to model the tag-lookup time. This "\ - "is only used when icache-state_modelled=true.") - icache_maintenance_latency = Param.UInt64(0, "L1 I-Cache timing "\ - "annotation latency for cache maintenance operations given in "\ - "total ticks. This is only used when icache-state_modelled=true.") - icache_miss_latency = Param.UInt64(0, "L1 I-Cache timing annotation "\ - "latency for miss. Intended to model the time for failed "\ - "tag-lookup and allocation of intermediate buffers. This is "\ - "only used when icache-state_modelled=true.") - icache_prefetch_enabled = Param.Bool(False, "Enable simulation of "\ - "instruction cache prefetching. This is only used when "\ - "icache-state_modelled=true.") - icache_read_access_latency = Param.UInt64(0, "L1 I-Cache timing "\ - "annotation latency for read accesses given in ticks per access "\ - "(of size icache-read_bus_width_in_bytes). If this parameter is "\ - "non-zero, per-access latencies will be used instead of per-byte "\ - "even if icache-read_latency is set. This is in addition to the "\ - "hit or miss latency, and intended to correspond to the time "\ - "taken to transfer across the cache upstream bus, this is only "\ - "used when icache-state_modelled=true.") - icache_read_latency = Param.UInt64(0, "L1 I-Cache timing annotation "\ - "latency for read accesses given in ticks per byte "\ - "accessed.icache-read_access_latency must be set to 0 for "\ - "per-byte latencies to be applied. This is in addition to the "\ - "hit or miss latency, and intended to correspond to the time "\ - "taken to transfer across the cache upstream bus. This is only "\ - "used when icache-state_modelled=true.") - icache_state_modelled = Param.Bool(False, - "Set whether I-cache has stateful implementation") - l3cache_hit_latency = Param.UInt64(0, "L3 Cache timing annotation "\ - "latency for hit. Intended to model the tag-lookup time. This "\ - "is only used when l3cache-state_modelled=true.") - l3cache_maintenance_latency = Param.UInt64(0, "L3 Cache timing "\ - "annotation latency for cache maintenance operations given in "\ - "total ticks. This is only used when dcache-state_modelled=true.") - l3cache_miss_latency = Param.UInt64(0, "L3 Cache timing annotation "\ - "latency for miss. Intended to model the time for failed "\ - "tag-lookup and allocation of intermediate buffers. This is "\ - "only used when l3cache-state_modelled=true.") - l3cache_read_access_latency = Param.UInt64(0, "L3 Cache timing "\ - "annotation latency for read accesses given in ticks per access "\ - "(of size l3cache-read_bus_width_in_bytes). If this parameter "\ - "is non-zero, per-access latencies will be used instead of "\ - "per-byte even if l3cache-read_latency is set. This is in "\ - "addition to the hit or miss latency, and intended to correspond "\ - "to the time taken to transfer across the cache upstream bus, "\ - "this is only used when l3cache-state_modelled=true.") - l3cache_read_latency = Param.UInt64(0, "L3 Cache timing annotation "\ - "latency for read accesses given in ticks per byte "\ - "accessed.l3cache-read_access_latency must be set to 0 for "\ - "per-byte latencies to be applied. This is in addition to the "\ - "hit or miss latency, and intended to correspond to the time "\ - "taken to transfer across the cache upstream bus. This is only "\ - "used when l3cache-state_modelled=true.") - l3cache_size = Param.MemorySize('0x100000', "L3 Cache size in bytes.") - l3cache_snoop_data_transfer_latency = Param.UInt64(0, "L3 Cache timing "\ - "annotation latency for received snoop accesses that perform a "\ - "data transfer given in ticks per byte accessed. This is only "\ - "used when dcache-state_modelled=true.") - l3cache_snoop_issue_latency = Param.UInt64(0, "L3 Cache timing "\ - "annotation latency for snoop accesses issued by this cache in "\ - "total ticks. This is only used when dcache-state_modelled=true.") - l3cache_write_access_latency = Param.UInt64(0, "L3 Cache timing "\ - "annotation latency for write accesses given in ticks per access "\ - "(of size l3cache-write_bus_width_in_bytes). If this parameter "\ - "is non-zero, per-access latencies will be used instead of "\ - "per-byte even if l3cache-write_latency is set. This is only "\ - "used when l3cache-state_modelled=true.") - l3cache_write_latency = Param.UInt64(0, "L3 Cache timing annotation "\ - "latency for write accesses given in ticks per byte accessed. "\ - "l3cache-write_access_latency must be set to 0 for per-byte "\ - "latencies to be applied. This is only used when "\ - "l3cache-state_modelled=true.") - pchannel_treat_simreset_as_poreset = Param.Bool(False, - "Register core as ON state to cluster with simulation reset.") - periph_address_end = Param.Addr(0x0, "End address for peripheral port "\ - "address range exclusive(corresponds to AENDMP input signal).") - periph_address_start = Param.Addr(0x0, "Start address for peripheral "\ - "port address range inclusive(corresponds to ASTARTMP input "\ - "signal).") - ptw_latency = Param.UInt64(0, "Page table walker latency for TA "\ - "(Timing Annotation), expressed in simulation ticks") - tlb_latency = Param.UInt64(0, "TLB latency for TA (Timing Annotation), "\ - "expressed in simulation ticks") - treat_dcache_cmos_to_pou_as_nop = Param.Bool(False, "Whether dcache "\ - "invalidation to the point of unification is required for "\ - "instruction to data coherence. true - Invalidate operations not "\ - "required") - walk_cache_latency = Param.UInt64(0, "Walk cache latency for TA (Timing "\ - "Annotation), expressed in simulation ticks") - -class FastModelScxEvsCortexA76x1(SystemC_ScModule): - type = 'FastModelScxEvsCortexA76x1' - cxx_class = 'FastModel::ScxEvsCortexA76x1' - cxx_header = 'arch/arm/fastmodel/CortexA76x1/cortex_a76x1.hh' - -class FastModelCortexA76x1(FastModelCortexA76Cluster): - cores = [ FastModelCortexA76(thread_paths=[ 'core.cpu0' ]) ] - - evs = FastModelScxEvsCortexA76x1() diff --git a/src/arch/arm/fastmodel/CortexA76x1/SConscript b/src/arch/arm/fastmodel/CortexA76x1/SConscript deleted file mode 100644 index a33049af4..000000000 --- a/src/arch/arm/fastmodel/CortexA76x1/SConscript +++ /dev/null @@ -1,41 +0,0 @@ -# Copyright 2019 Google, Inc. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are -# met: redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer; -# redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution; -# neither the name of the copyright holders nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -# Authors: Gabe Black - -Import('*') - -if not env['USE_ARM_FASTMODEL'] or env['TARGET_ISA'] != 'arm': - Return() - -protocol_dir = Dir('..').Dir('protocol') - -ArmFastModelComponent(File('CortexA76x1.sgproj'), - File('CortexA76x1.lisa'), - protocol_dir.File( - 'ExportedClockRateControlProtocol.lisa') - ).prepare_env(env) -SimObject('FastModelCortexA76x1.py') -Source('cortex_a76x1.cc') diff --git a/src/arch/arm/fastmodel/CortexA76x1/cortex_a76x1.cc b/src/arch/arm/fastmodel/CortexA76x1/cortex_a76x1.cc deleted file mode 100644 index 898082741..000000000 --- a/src/arch/arm/fastmodel/CortexA76x1/cortex_a76x1.cc +++ /dev/null @@ -1,312 +0,0 @@ -/* - * Copyright 2019 Google, Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Gabe Black - */ - -#include "arch/arm/fastmodel/CortexA76x1/cortex_a76x1.hh" - -#include "arch/arm/fastmodel/arm/cpu.hh" -#include "arch/arm/fastmodel/iris/cpu.hh" -#include "base/logging.hh" -#include "dev/arm/base_gic.hh" -#include "sim/core.hh" -#include "systemc/tlm_bridge/gem5_to_tlm.hh" - -namespace FastModel -{ - -void -CortexA76::setCluster(CortexA76Cluster *_cluster, int _num) -{ - cluster = _cluster; - num = _num; - - set_evs_param("CFGEND", params().CFGEND); - set_evs_param("CFGTE", params().CFGTE); - set_evs_param("CRYPTODISABLE", params().CRYPTODISABLE); - set_evs_param("RVBARADDR", params().RVBARADDR); - set_evs_param("VINITHI", params().VINITHI); - set_evs_param("enable_trace_special_hlt_imm16", - params().enable_trace_special_hlt_imm16); - set_evs_param("l2cache-hit_latency", params().l2cache_hit_latency); - set_evs_param("l2cache-maintenance_latency", - params().l2cache_maintenance_latency); - set_evs_param("l2cache-miss_latency", params().l2cache_miss_latency); - set_evs_param("l2cache-read_access_latency", - params().l2cache_read_access_latency); - set_evs_param("l2cache-read_latency", params().l2cache_read_latency); - set_evs_param("l2cache-size", params().l2cache_size); - set_evs_param("l2cache-snoop_data_transfer_latency", - params().l2cache_snoop_data_transfer_latency); - set_evs_param("l2cache-snoop_issue_latency", - params().l2cache_snoop_issue_latency); - set_evs_param("l2cache-write_access_latency", - params().l2cache_write_access_latency); - set_evs_param("l2cache-write_latency", params().l2cache_write_latency); - set_evs_param("max_code_cache_mb", params().max_code_cache_mb); - set_evs_param("min_sync_level", params().min_sync_level); - set_evs_param("semihosting-A32_HLT", params().semihosting_A32_HLT); - set_evs_param("semihosting-A64_HLT", params().semihosting_A64_HLT); - set_evs_param("semihosting-ARM_SVC", params().semihosting_ARM_SVC); - set_evs_param("semihosting-T32_HLT", params().semihosting_T32_HLT); - set_evs_param("semihosting-Thumb_SVC", params().semihosting_Thumb_SVC); - set_evs_param("semihosting-cmd_line", params().semihosting_cmd_line); - set_evs_param("semihosting-cwd", params().semihosting_cwd); - set_evs_param("semihosting-enable", params().semihosting_enable); - set_evs_param("semihosting-heap_base", params().semihosting_heap_base); - set_evs_param("semihosting-heap_limit", params().semihosting_heap_limit); - set_evs_param("semihosting-stack_base", params().semihosting_stack_base); - set_evs_param("semihosting-stack_limit", params().semihosting_stack_limit); - set_evs_param("trace_special_hlt_imm16", params().trace_special_hlt_imm16); - set_evs_param("vfp-enable_at_reset", params().vfp_enable_at_reset); -} - -Port & -CortexA76::getPort(const std::string &if_name, PortID idx) -{ - if (if_name == "redistributor") - return cluster->getEvs()->gem5_getPort(if_name, num); - else - return ArmCPU::getPort(if_name, idx); -} - -CortexA76Cluster::CortexA76Cluster(Params &p) : - SimObject(&p), _params(p), cores(p.cores), evs(p.evs) -{ - for (int i = 0; i < p.cores.size(); i++) - p.cores[i]->setCluster(this, i); - - sc_core::sc_attr_base *base; - - base = evs->get_attribute(Iris::Gem5CpuClusterAttributeName); - auto *gem5_cluster_attr = - dynamic_cast *>(base); - panic_if(base && !gem5_cluster_attr, - "The EVS gem5 CPU cluster attribute was not of type " - "sc_attribute."); - if (gem5_cluster_attr) - gem5_cluster_attr->value = this; - - set_evs_param("core.BROADCASTATOMIC", p.BROADCASTATOMIC); - set_evs_param("core.BROADCASTCACHEMAINT", p.BROADCASTCACHEMAINT); - set_evs_param("core.BROADCASTOUTER", p.BROADCASTOUTER); - set_evs_param("core.BROADCASTPERSIST", p.BROADCASTPERSIST); - set_evs_param("core.CLUSTER_ID", p.CLUSTER_ID); - set_evs_param("core.GICDISABLE", p.GICDISABLE); - set_evs_param("core.cpi_div", p.cpi_div); - set_evs_param("core.cpi_mul", p.cpi_mul); - set_evs_param("core.dcache-hit_latency", p.dcache_hit_latency); - set_evs_param("core.dcache-maintenance_latency", - p.dcache_maintenance_latency); - set_evs_param("core.dcache-miss_latency", p.dcache_miss_latency); - set_evs_param("core.dcache-prefetch_enabled", - p.dcache_prefetch_enabled); - set_evs_param("core.dcache-read_access_latency", - p.dcache_read_access_latency); - set_evs_param("core.dcache-read_latency", p.dcache_read_latency); - set_evs_param("core.dcache-snoop_data_transfer_latency", - p.dcache_snoop_data_transfer_latency); - set_evs_param("core.dcache-state_modelled", p.dcache_state_modelled); - set_evs_param("core.dcache-write_access_latency", - p.dcache_write_access_latency); - set_evs_param("core.dcache-write_latency", p.dcache_write_latency); - set_evs_param("core.default_opmode", p.default_opmode); - set_evs_param("core.diagnostics", p.diagnostics); - set_evs_param("core.enable_simulation_performance_optimizations", - p.enable_simulation_performance_optimizations); - set_evs_param("core.ext_abort_device_read_is_sync", - p.ext_abort_device_read_is_sync); - set_evs_param("core.ext_abort_device_write_is_sync", - p.ext_abort_device_write_is_sync); - set_evs_param("core.ext_abort_so_read_is_sync", - p.ext_abort_so_read_is_sync); - set_evs_param("core.ext_abort_so_write_is_sync", - p.ext_abort_so_write_is_sync); - set_evs_param("core.gicv3.cpuintf-mmap-access-level", - p.gicv3_cpuintf_mmap_access_level); - set_evs_param("core.has_peripheral_port", p.has_peripheral_port); - set_evs_param("core.has_statistical_profiling", - p.has_statistical_profiling); - set_evs_param("core.icache-hit_latency", p.icache_hit_latency); - set_evs_param("core.icache-maintenance_latency", - p.icache_maintenance_latency); - set_evs_param("core.icache-miss_latency", p.icache_miss_latency); - set_evs_param("core.icache-prefetch_enabled", - p.icache_prefetch_enabled); - set_evs_param("core.icache-read_access_latency", - p.icache_read_access_latency); - set_evs_param("core.icache-read_latency", p.icache_read_latency); - set_evs_param("core.icache-state_modelled", p.icache_state_modelled); - set_evs_param("core.l3cache-hit_latency", p.l3cache_hit_latency); - set_evs_param("core.l3cache-maintenance_latency", - p.l3cache_maintenance_latency); - set_evs_param("core.l3cache-miss_latency", p.l3cache_miss_latency); - set_evs_param("core.l3cache-read_access_latency", - p.l3cache_read_access_latency); - set_evs_param("core.l3cache-read_latency", p.l3cache_read_latency); - set_evs_param("core.l3cache-size", p.l3cache_size); - set_evs_param("core.l3cache-snoop_data_transfer_latency", - p.l3cache_snoop_data_transfer_latency); - set_evs_param("core.l3cache-snoop_issue_latency", - p.l3cache_snoop_issue_latency); - set_evs_param("core.l3cache-write_access_latency", - p.l3cache_write_access_latency); - set_evs_param("core.l3cache-write_latency", p.l3cache_write_latency); - set_evs_param("core.pchannel_treat_simreset_as_poreset", - p.pchannel_treat_simreset_as_poreset); - set_evs_param("core.periph_address_end", p.periph_address_end); - set_evs_param("core.periph_address_start", p.periph_address_start); - set_evs_param("core.ptw_latency", p.ptw_latency); - set_evs_param("core.tlb_latency", p.tlb_latency); - set_evs_param("core.treat-dcache-cmos-to-pou-as-nop", - p.treat_dcache_cmos_to_pou_as_nop); - set_evs_param("core.walk_cache_latency", p.walk_cache_latency); -} - -Port & -CortexA76Cluster::getPort(const std::string &if_name, PortID idx) -{ - if (if_name == "amba") { - return evs->gem5_getPort(if_name, idx); - } else { - return SimObject::getPort(if_name, idx); - } -} - -void -ScxEvsCortexA76x1::clockChangeHandler() -{ - clockRateControl->set_mul_div(SimClock::Int::s, clockPeriod.value); -} - -ScxEvsCortexA76x1::ScxEvsCortexA76x1(const sc_core::sc_module_name &mod_name, - const Params &p) : - scx_evs_CortexA76x1(mod_name), - amba(scx_evs_CortexA76x1::amba, p.name + ".amba", -1), - redist { - new TlmGicTarget(redistributor[0], - csprintf("%s.redistributor[%d]", name(), 0), 0) - }, - cnthpirq("cnthpirq"), cnthvirq("cnthvirq"), cntpsirq("cntpsirq"), - cntvirq("cntvirq"), commirq("commirq"), ctidbgirq("ctidbgirq"), - pmuirq("pmuirq"), vcpumntirq("vcpumntirq"), cntpnsirq("cntpnsirq"), - clockChanged(Iris::ClockEventName.c_str()), - clockPeriod(Iris::PeriodAttributeName.c_str()), - gem5CpuCluster(Iris::Gem5CpuClusterAttributeName.c_str()), - sendFunctional(Iris::SendFunctionalAttributeName.c_str()), - params(p) -{ - clockRateControl.bind(clock_rate_s); - - add_attribute(gem5CpuCluster); - add_attribute(clockPeriod); - SC_METHOD(clockChangeHandler); - dont_initialize(); - sensitive << clockChanged; - - scx_evs_CortexA76x1::cnthpirq[0].bind(cnthpirq.signal_in); - scx_evs_CortexA76x1::cnthvirq[0].bind(cnthvirq.signal_in); - scx_evs_CortexA76x1::cntpsirq[0].bind(cntpsirq.signal_in); - scx_evs_CortexA76x1::cntvirq[0].bind(cntvirq.signal_in); - scx_evs_CortexA76x1::commirq[0].bind(commirq.signal_in); - scx_evs_CortexA76x1::ctidbgirq[0].bind(ctidbgirq.signal_in); - scx_evs_CortexA76x1::pmuirq[0].bind(pmuirq.signal_in); - scx_evs_CortexA76x1::vcpumntirq[0].bind(vcpumntirq.signal_in); - scx_evs_CortexA76x1::cntpnsirq[0].bind(cntpnsirq.signal_in); - - sendFunctional.value = [this](PacketPtr pkt) { sendFunc(pkt); }; - add_attribute(sendFunctional); -} - -void -ScxEvsCortexA76x1::sendFunc(PacketPtr pkt) -{ - auto *trans = sc_gem5::packet2payload(pkt); - panic_if(scx_evs_CortexA76x1::amba->transport_dbg(*trans) != - trans->get_data_length(), "Didn't send entire functional packet!"); - trans->release(); -} - -void -ScxEvsCortexA76x1::before_end_of_elaboration() -{ - scx_evs_CortexA76x1::before_end_of_elaboration(); - - auto *cluster = gem5CpuCluster.value; - - auto set_on_change = [cluster]( - SignalReceiver &recv, ArmInterruptPinGen *gen, int num) - { - auto *pin = gen->get(cluster->getCore(num)->getContext(0)); - auto handler = [pin](bool status) - { - status ? pin->raise() : pin->clear(); - }; - recv.onChange(handler); - }; - - set_on_change(cnthpirq, cluster->params().cnthpirq, 0); - set_on_change(cnthvirq, cluster->params().cnthvirq, 0); - set_on_change(cntpsirq, cluster->params().cntpsirq, 0); - set_on_change(cntvirq, cluster->params().cntvirq, 0); - set_on_change(commirq, cluster->params().commirq, 0); - set_on_change(ctidbgirq, cluster->params().ctidbgirq, 0); - set_on_change(pmuirq, cluster->params().pmuirq, 0); - set_on_change(vcpumntirq, cluster->params().vcpumntirq, 0); - set_on_change(cntpnsirq, cluster->params().cntpnsirq, 0); -} - -Port & -ScxEvsCortexA76x1::gem5_getPort(const std::string &if_name, int idx) -{ - if (if_name == "redistributor") - return *redist.at(idx); - else if (if_name == "amba") - return amba; - else - return scx_evs_CortexA76x1::gem5_getPort(if_name, idx); -} - -} // namespace FastModel - -FastModel::CortexA76 * -FastModelCortexA76Params::create() -{ - return new FastModel::CortexA76(*this); -} - -FastModel::CortexA76Cluster * -FastModelCortexA76ClusterParams::create() -{ - return new FastModel::CortexA76Cluster(*this); -} - -FastModel::ScxEvsCortexA76x1 * -FastModelScxEvsCortexA76x1Params::create() -{ - return new FastModel::ScxEvsCortexA76x1(name.c_str(), *this); -} diff --git a/src/arch/arm/fastmodel/CortexA76x1/cortex_a76x1.hh b/src/arch/arm/fastmodel/CortexA76x1/cortex_a76x1.hh deleted file mode 100644 index 096991ad8..000000000 --- a/src/arch/arm/fastmodel/CortexA76x1/cortex_a76x1.hh +++ /dev/null @@ -1,170 +0,0 @@ -/* - * Copyright 2019 Google, Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Gabe Black - */ - -#ifndef __ARCH_ARM_FASTMODEL_CORTEXA76X1_CORETEX_A76X1_HH__ -#define __ARCH_ARM_FASTMODEL_CORTEXA76X1_CORETEX_A76X1_HH__ - -#include "arch/arm/fastmodel/amba_ports.hh" -#include "arch/arm/fastmodel/arm/cpu.hh" -#include "arch/arm/fastmodel/common/signal_receiver.hh" -#include "arch/arm/fastmodel/protocol/exported_clock_rate_control.hh" -#include "mem/port_proxy.hh" -#include "params/FastModelCortexA76.hh" -#include "params/FastModelCortexA76Cluster.hh" -#include "params/FastModelScxEvsCortexA76x1.hh" -#include "scx_evs_CortexA76x1.h" -#include "systemc/ext/core/sc_event.hh" -#include "systemc/ext/core/sc_module.hh" - -class BaseCPU; - -namespace FastModel -{ - -// The fast model exports a class called scx_evs_CortexA76x1 which represents -// the subsystem described in LISA+. This class specializes it to export gem5 -// ports and interface with its peer gem5 CPU. The gem5 CPU inherits from the -// gem5 BaseCPU class and implements its API, while this class actually does -// the work. -class CortexA76Cluster; - -class CortexA76 : public ArmCPU -{ - protected: - typedef FastModelCortexA76Params Params; - const Params &_params; - - CortexA76Cluster *cluster = nullptr; - int num = 0; - - const Params ¶ms() { return _params; } - - public: - CortexA76(Params &p) : ArmCPU(&p), _params(p) {} - - template - void set_evs_param(const std::string &n, T val); - - void setCluster(CortexA76Cluster *_cluster, int _num); - - Port &getPort(const std::string &if_name, - PortID idx=InvalidPortID) override; -}; - -class CortexA76Cluster : public SimObject -{ - private: - typedef FastModelCortexA76ClusterParams Params; - const Params &_params; - - std::vector cores; - sc_core::sc_module *evs; - - public: - template - void - set_evs_param(const std::string &n, T val) - { - scx::scx_set_parameter(evs->name() + std::string(".") + n, val); - } - - CortexA76 *getCore(int num) { return cores.at(num); } - sc_core::sc_module *getEvs() { return evs; } - - CortexA76Cluster(Params &p); - const Params ¶ms() { return _params; } - - Port &getPort(const std::string &if_name, - PortID idx=InvalidPortID) override; -}; - -class ScxEvsCortexA76x1 : public scx_evs_CortexA76x1 -{ - private: - SC_HAS_PROCESS(ScxEvsCortexA76x1); - - ClockRateControlInitiatorSocket clockRateControl; - - typedef sc_gem5::TlmTargetBaseWrapper< - 64, svp_gicv3_comms::gicv3_comms_fw_if, - svp_gicv3_comms::gicv3_comms_bw_if, 1, - sc_core::SC_ONE_OR_MORE_BOUND> TlmGicTarget; - - AmbaInitiator amba; - std::vector redist; - - SignalReceiver cnthpirq; - SignalReceiver cnthvirq; - SignalReceiver cntpsirq; - SignalReceiver cntvirq; - SignalReceiver commirq; - SignalReceiver ctidbgirq; - SignalReceiver pmuirq; - SignalReceiver vcpumntirq; - SignalReceiver cntpnsirq; - - sc_core::sc_event clockChanged; - sc_core::sc_attribute clockPeriod; - sc_core::sc_attribute gem5CpuCluster; - sc_core::sc_attribute sendFunctional; - - void sendFunc(PacketPtr pkt); - - void clockChangeHandler(); - - typedef FastModelScxEvsCortexA76x1Params Params; - const Params ¶ms; - - public: - ScxEvsCortexA76x1( - const sc_core::sc_module_name &mod_name, const Params &p); - - void before_end_of_elaboration() override; - Port &gem5_getPort(const std::string &if_name, int idx) override; - - void - end_of_elaboration() override - { - scx_evs_CortexA76x1::end_of_elaboration(); - scx_evs_CortexA76x1::start_of_simulation(); - } - void start_of_simulation() override {} -}; - -template -inline void -CortexA76::set_evs_param(const std::string &n, T val) -{ - for (auto &path: params().thread_paths) - cluster->set_evs_param(path + "." + n, val); -} - -} // namespace FastModel - -#endif // __ARCH_ARM_FASTMODEL_CORTEXA76X1_CORETEX_A76X1_HH__