From: Sandipan Das <sandipan@linux.vnet.ibm.com>
Date: Thu, 7 Jun 2018 09:30:27 +0000 (+0530)
Subject: arch-power: Add fixed-point logical extend sign instructions
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=eb592fe78db092d033035c1d2126cca2723188e3;p=gem5.git

arch-power: Add fixed-point logical extend sign instructions

This adds the following logical instructions:
  * Extend Sign Word (extsw[.])

Change-Id: I610e84c2361b99b00ceef2170ede5b6dee8ec21b
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
---

diff --git a/src/arch/power/insts/integer.cc b/src/arch/power/insts/integer.cc
index 4f2804f9c..b49da47e1 100644
--- a/src/arch/power/insts/integer.cc
+++ b/src/arch/power/insts/integer.cc
@@ -294,6 +294,7 @@ IntLogicOp::generateDisassembly(
         printSecondSrc = false;
     } else if (!myMnemonic.compare("extsb") ||
                !myMnemonic.compare("extsh") ||
+               !myMnemonic.compare("extsw") ||
                !myMnemonic.compare("cntlzw")) {
         printSecondSrc = false;
     }
diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index 77ce3c04c..6575f4f54 100644
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -511,6 +511,7 @@ decode PO default Unknown::unknown() {
             412: orc({{ Ra = Rs | ~Rb; }}, true);
             954: extsb({{ Ra = Rs_sb; }}, true);
             922: extsh({{ Ra = Rs_sh; }}, true);
+            986: extsw({{ Ra = Rs_sw; }}, true);
             26: cntlzw({{ Ra = findLeadingZeros(Rs_uw); }}, true);
 
             508: cmpb({{