From: Cesar Strauss <cestrauss@gmail.com>
Date: Wed, 18 Nov 2020 10:59:15 +0000 (-0300)
Subject: Separate individual traces for each rel_o/go_i port
X-Git-Tag: 24jan2021_ls180~89
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=eb5c03ef711b4501c517aa1cfd91ef3c31595a31;p=soc.git

Separate individual traces for each rel_o/go_i port

Use the new "bit" attribute to select individual bits from the
wide rel_o/go_i signals.
---

diff --git a/src/soc/experiment/test/test_compalu_multi.py b/src/soc/experiment/test/test_compalu_multi.py
index cc22f601..4c6cbe6d 100644
--- a/src/soc/experiment/test/test_compalu_multi.py
+++ b/src/soc/experiment/test/test_compalu_multi.py
@@ -306,9 +306,20 @@ def scoreboard_sim(dut):
 def test_compunit_fsm():
     top = "top.cu" if is_engine_pysim() else "cu"
     traces = [
-        'clk', 'src1_i[7:0]', 'src2_i[7:0]', 'oper_i_None__sdir', 'cu_issue_i',
-        'cu_busy_o', 'cu_rd__rel_o[1:0]', 'cu_rd__go_i[1:0]',
-        'cu_wr__rel_o', 'cu_wr__go_i', 'dest1_o[7:0]',
+        'clk',
+        ('operation port', {'color': 'red'}, [
+            'oper_i_None__sdir', 'cu_issue_i',
+            'cu_busy_o']),
+        ('operand 1 port', {'color': 'yellow'}, [
+            ('cu_rd__rel_o[1:0]', {'bit': 1}),
+            ('cu_rd__go_i[1:0]', {'bit': 1}),
+            'src1_i[7:0]']),
+        ('operand 2 port', {'color': 'yellow'}, [
+            ('cu_rd__rel_o[1:0]', {'bit': 0}),
+            ('cu_rd__go_i[1:0]', {'bit': 0}),
+            'src2_i[7:0]']),
+        ('result port', {'color': 'orange'}, [
+            'cu_wr__rel_o', 'cu_wr__go_i', 'dest1_o[7:0]']),
         ('alu', {'module': top+'.alu'}, [
             'p_data_i[7:0]', 'p_shift_i[7:0]', 'op__sdir',
             'p_valid_i', 'p_ready_o', 'n_valid_o', 'n_ready_i',