From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 15 Apr 2019 05:12:06 +0000 (+0100)
Subject: tidyup
X-Git-Tag: div_pipeline~2228
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=eb5fdf601c4fbefff419d6efe19a3dcdf4566cfe;p=soc.git

tidyup
---

diff --git a/TLB/src/ariane/ptw.py b/TLB/src/ariane/ptw.py
index fbd2dc21..8bd3cbea 100644
--- a/TLB/src/ariane/ptw.py
+++ b/TLB/src/ariane/ptw.py
@@ -23,11 +23,14 @@ from nmigen.hdl.ast import ArrayProxy
 from nmigen.cli import verilog, rtlil
 from math import log2
 
+
 DCACHE_SET_ASSOC = 8
 CONFIG_L1D_SIZE =  32*1024
 DCACHE_INDEX_WIDTH = int(log2(CONFIG_L1D_SIZE / DCACHE_SET_ASSOC))
 DCACHE_TAG_WIDTH = 56 - DCACHE_INDEX_WIDTH
 
+ASID_WIDTH = 8
+
 
 class DCacheReqI:
     def __init__(self):
@@ -58,8 +61,6 @@ class DCacheReqO:
         return [ self.data_gnt, self.data_rvalid, self.data_rdata]
 
 
-ASID_WIDTH = 8
-
 class PTE: #(RecordObject):
     def __init__(self):
         self.reserved = Signal(10)
@@ -182,7 +183,7 @@ class PTW:
         m.d.comb += pte.flatten().eq(data_rdata)
 
         # SV39 defines three levels of page tables
-        ptw_lvl = Signal(2) # default=0=LVL1
+        ptw_lvl = Signal(2) # default=0=LVL1 on reset (see above)
         ptw_lvl1 = Signal()
         ptw_lvl2 = Signal()
         ptw_lvl3 = Signal()