From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 30 Jul 2018 06:19:26 +0000 (+0100)
Subject: vectorise pincon sync
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=eb6cfab95e4041dd2b12a0a484c51611e814c802;p=pinmux.git

vectorise pincon sync
---

diff --git a/src/bsv/peripheral_gen/base.py b/src/bsv/peripheral_gen/base.py
index 7b8ca98..fd30384 100644
--- a/src/bsv/peripheral_gen/base.py
+++ b/src/bsv/peripheral_gen/base.py
@@ -196,6 +196,20 @@ else"""
                     ret += cn
         return '\n'.join(ret)
 
+    def _mk_vpincon(self, name, count, ptyp, typ, pname):
+        ret = []
+        if ptyp == 'fast':
+            sname = self.get_iname(count)
+            ps = "slow_peripherals.%s" % sname
+        else:
+            sname = self.peripheral.iname().format(count)
+            ps = "pinmux.peripheral_side.%s" % sname
+        n = self.get_iname(count)
+        ps_ = "{0}.{1}".format(ps, pname)
+        ret += self._mk_actual_connection(typ, name, count, typ,
+                                          pname, ps_, n, pname)
+        return '\n'.join(ret)
+
     def _mk_actual_connection(self, ctype, name, count, typ,
                               pname, ps, n, fname):
         ret = []
@@ -227,6 +241,7 @@ else"""
                             sync, n))
         return ret
 
+
     def _mk_clk_con(self, name, count, ctype):
         ret = []
         ck = self.get_clock_reset(name, count)
@@ -265,6 +280,23 @@ Ifc_sync#({0}) {1}_sync <-mksyncconnection(
                 ret.append(template.format("Bit#(1)", n_, spc, ck))
         return '\n'.join(ret)
 
+    def _mk_clk_vcon(self, name, count, ctype, typ, pname, bitspec):
+        ck = self.get_clock_reset(name, count)
+        if ck == PBase.get_clock_reset(self, name, count):
+            return ''
+        if ctype == 'slow':
+            spc = "sp_clock, sp_reset"
+        else:
+            spc = ck
+            ck = "core_clock, core_reset"
+        template = """\
+Ifc_sync#({0}) {1}_sync <-mksyncconnection(
+            {2}, {3});"""
+
+        n_ = "{0}{1}".format(name, count)
+        n_ = '{0}_{1}'.format(n_, pname)
+        return template.format(bitspec,  n_, ck, spc)
+
 
     def mk_cellconn(self, *args):
         return ''
diff --git a/src/bsv/peripheral_gen/rgbttl.py b/src/bsv/peripheral_gen/rgbttl.py
index 91f2eb9..9c917e7 100644
--- a/src/bsv/peripheral_gen/rgbttl.py
+++ b/src/bsv/peripheral_gen/rgbttl.py
@@ -29,39 +29,16 @@ class rgbttl(PBase):
 
     def _mk_pincon(self, name, count, ptyp):
         ret = [PBase._mk_pincon(self, name, count, ptyp)]
-        if ptyp == 'fast':
-            sname = self.get_iname(count)
-            ps = "slow_peripherals.%s" % sname
-        else:
-            sname = self.peripheral.iname().format(count)
-            ps = "pinmux.peripheral_side.%s" % sname
-        n = self.get_iname(count)
-        for ptype in ['data_out']:
-            ps_ = "{0}.{1}".format(ps, ptype)
-            ret += self._mk_actual_connection('out', name, count, 'out',
-                                              ptype, ps_, n, ptype)
+        txt = self._mk_vpincon(name, count, ptyp, "out", "data_out")
+        ret.append(txt)
         return '\n'.join(ret)
 
     def _mk_clk_con(self, name, count, ctype):
         ret = [PBase._mk_clk_con(self, name, count, ctype)]
-        ck = self.get_clock_reset(name, count)
-        if ck == PBase.get_clock_reset(self, name, count):
-            return ret
-        if ctype == 'slow':
-            spc = "sp_clock, sp_reset"
-        else:
-            spc = ck
-            ck = "core_clock, core_reset"
-        template = """\
-Ifc_sync#({0}) {1}_sync <-mksyncconnection(
-            {2}, {3});"""
 
-        # one pin, data_out, might as well hard-code it
-        typ = 'out'
-        pname = 'data_out'
-        n = name
-        n_ = "{0}{1}".format(n, count)
-        n_ = '{0}_{1}'.format(n_, pname)
+        # data_out (hard-coded)
         sz = len(self.peripheral.pinspecs) - 4  # subtract CK, DE, HS, VS
-        ret.append(template.format("Bit#(%d)" % sz, n_, ck, spc))
+        bitspec = "Bit#(%d)" % sz
+        txt = self._mk_clk_vcon(name, count, ctype, "out", "data_out", bitspec)
+        ret.append(txt)
         return '\n'.join(ret)