From: Gabe Black Date: Mon, 18 Jan 2021 01:40:57 +0000 (-0800) Subject: arm: Export the mostly generic syscall ABI. X-Git-Tag: develop-gem5-snapshot~271 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=eb7958c6e20f2f225c8f1b9cc1cfcfa28abfb7cd;p=gem5.git arm: Export the mostly generic syscall ABI. This ABI is also applicable for gem5 ops. Rather than have the gem5 ops use the syscall ABI, this change exports the syscall ABI and renames it the "reg" ABI, or in other words an ABI which only uses registers. The SE workload class then just creates a local name for the "reg" ABI so it can continue to use it for system calls. Change-Id: Ifaa38a94d6f0d49b8a2e515e02ce94472a499a00 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39315 Reviewed-by: Giacomo Travaglini Maintainer: Giacomo Travaglini Tested-by: kokoro --- diff --git a/src/arch/arm/SConscript b/src/arch/arm/SConscript index 31e83a778..1d6799e27 100644 --- a/src/arch/arm/SConscript +++ b/src/arch/arm/SConscript @@ -89,11 +89,11 @@ if env['TARGET_ISA'] == 'arm': Source('process.cc') Source('qarma.cc') Source('remote_gdb.cc') + Source('reg_abi.cc') Source('semihosting.cc') Source('system.cc') Source('table_walker.cc') Source('self_debug.cc') - Source('se_workload.cc') Source('stage2_mmu.cc') Source('stage2_lookup.cc') Source('tlb.cc') diff --git a/src/arch/arm/reg_abi.cc b/src/arch/arm/reg_abi.cc new file mode 100644 index 000000000..ba1511c26 --- /dev/null +++ b/src/arch/arm/reg_abi.cc @@ -0,0 +1,36 @@ +/* + * Copyright 2020 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "arch/arm/reg_abi.hh" + +namespace ArmISA +{ + +const std::vector RegABI32::ArgumentRegs = {0, 1, 2, 3, 4, 5, 6}; +const std::vector RegABI64::ArgumentRegs = {0, 1, 2, 3, 4, 5, 6}; + +} // namespace ArmISA diff --git a/src/arch/arm/reg_abi.hh b/src/arch/arm/reg_abi.hh new file mode 100644 index 000000000..eb87eff77 --- /dev/null +++ b/src/arch/arm/reg_abi.hh @@ -0,0 +1,76 @@ +/* + * Copyright 2020 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __ARCH_ARM_REG_ABI_HH__ +#define __ARCH_ARM_REG_ABI_HH__ + +#include + +#include "base/logging.hh" +#include "sim/syscall_abi.hh" + +namespace ArmISA +{ + +struct RegABI32 : public GenericSyscallABI32 +{ + static const std::vector ArgumentRegs; +}; + +struct RegABI64 : public GenericSyscallABI64 +{ + static const std::vector ArgumentRegs; +}; + +} // namespace ArmISA + +namespace GuestABI +{ + +template +struct Argument::value && + ABI::template IsWide::value>> +{ + static Arg + get(ThreadContext *tc, typename ABI::State &state) + { + // 64 bit arguments are passed starting in an even register. + if (state % 2) + state++; + panic_if(state + 1 >= ABI::ArgumentRegs.size(), + "Ran out of syscall argument registers."); + auto low = ABI::ArgumentRegs[state++]; + auto high = ABI::ArgumentRegs[state++]; + return (Arg)ABI::mergeRegs(tc, low, high); + } +}; + +} // namespace GuestABI + +#endif // __ARCH_ARM_GEM5_OP_HH__ diff --git a/src/arch/arm/se_workload.cc b/src/arch/arm/se_workload.cc deleted file mode 100644 index 72abb8d14..000000000 --- a/src/arch/arm/se_workload.cc +++ /dev/null @@ -1,41 +0,0 @@ -/* - * Copyright 2020 Google Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "arch/arm/se_workload.hh" - -namespace ArmISA -{ - -const std::vector SEWorkload::SyscallABI32::ArgumentRegs = { - 0, 1, 2, 3, 4, 5, 6 -}; - -const std::vector SEWorkload::SyscallABI64::ArgumentRegs = { - 0, 1, 2, 3, 4, 5, 6 -}; - -} // namespace ArmISA diff --git a/src/arch/arm/se_workload.hh b/src/arch/arm/se_workload.hh index cad350e1e..8538edd48 100644 --- a/src/arch/arm/se_workload.hh +++ b/src/arch/arm/se_workload.hh @@ -28,10 +28,9 @@ #ifndef __ARCH_ARM_SE_WORKLOAD_HH__ #define __ARCH_ARM_SE_WORKLOAD_HH__ +#include "arch/arm/reg_abi.hh" #include "params/ArmSEWorkload.hh" #include "sim/se_workload.hh" -#include "sim/syscall_abi.hh" -#include "sim/syscall_desc.hh" namespace ArmISA { @@ -51,42 +50,10 @@ class SEWorkload : public ::SEWorkload ::Loader::Arch getArch() const override { return ::Loader::Arm64; } - struct SyscallABI32 : public GenericSyscallABI32 - { - static const std::vector ArgumentRegs; - }; - - struct SyscallABI64 : public GenericSyscallABI64 - { - static const std::vector ArgumentRegs; - }; + using SyscallABI32 = RegABI32; + using SyscallABI64 = RegABI64; }; } // namespace ArmISA -namespace GuestABI -{ - -template -struct Argument::value && - ABI::template IsWide::value>> -{ - static Arg - get(ThreadContext *tc, typename ABI::State &state) - { - // 64 bit arguments are passed starting in an even register. - if (state % 2) - state++; - panic_if(state + 1 >= ABI::ArgumentRegs.size(), - "Ran out of syscall argument registers."); - auto low = ABI::ArgumentRegs[state++]; - auto high = ABI::ArgumentRegs[state++]; - return (Arg)ABI::mergeRegs(tc, low, high); - } -}; - -} // namespace GuestABI - #endif // __ARCH_ARM_SE_WORKLOAD_HH__