From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 11 Feb 2017 10:09:07 +0000 (+0100)
Subject: Fix extremely stupid typo
X-Git-Tag: yosys-0.8~502
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=eb7b18e897ac908e960bee6c976f744043590881;p=yosys.git

Fix extremely stupid typo
---

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 3f5cf3f5f..306bc5d82 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -774,7 +774,7 @@ struct VerificImporter
 
 				SigBit outsig = net_map.at(out);
 				log_assert(outsig.wire && GetSize(outsig.wire) == 1);
-				outsig.wire->attributes["\\init"] == Const(0, 1);
+				outsig.wire->attributes["\\init"] = Const(0, 1);
 
 				module->addDff(NEW_ID, net_map.at(clk), net_map.at(in2), net_map.at(out));
 				continue;