From: Andreas Sandberg <andreas.sandberg@arm.com>
Date: Wed, 10 Aug 2016 15:26:34 +0000 (+0100)
Subject: arm, config: Add initial support for Ruby
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=eb87ed8e7458c3214d4163a7dbb180110b375d98;p=gem5.git

arm, config: Add initial support for Ruby

Add initial support for creating an ARM system with a Ruby-based
memory system. This support is currently experimental and limited to
the new VExpress_GEM5_V1 platform.

Change-Id: I36baeb68b0d891e34ea46aafe17b5e55217b4bfa
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Brad Beckmann <brad.beckmann@amd.com>
---

diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py
index e6dcac8a4..33b51b4f4 100644
--- a/configs/common/FSConfig.py
+++ b/configs/common/FSConfig.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2010-2012, 2015 ARM Limited
+# Copyright (c) 2010-2012, 2015-2016 ARM Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -203,7 +203,7 @@ def makeSparcSystem(mem_mode, mdesc=None, cmdline=None):
 
 def makeArmSystem(mem_mode, machine_type, num_cpus=1, mdesc=None,
                   dtb_filename=None, bare_metal=False, cmdline=None,
-                  external_memory=""):
+                  external_memory="", ruby=False):
     assert machine_type
 
     default_dtbs = {
@@ -233,11 +233,12 @@ def makeArmSystem(mem_mode, machine_type, num_cpus=1, mdesc=None,
 
     self.readfile = mdesc.script()
     self.iobus = IOXBar()
-    self.membus = MemBus()
-    self.membus.badaddr_responder.warn_access = "warn"
-    self.bridge = Bridge(delay='50ns')
-    self.bridge.master = self.iobus.slave
-    self.bridge.slave = self.membus.master
+    if not ruby:
+        self.bridge = Bridge(delay='50ns')
+        self.bridge.master = self.iobus.slave
+        self.membus = MemBus()
+        self.membus.badaddr_responder.warn_access = "warn"
+        self.bridge.slave = self.membus.master
 
     self.mem_mode = mem_mode
 
@@ -318,7 +319,7 @@ def makeArmSystem(mem_mode, machine_type, num_cpus=1, mdesc=None,
         # iobus, as gem5's membus is only used for initialization and
         # SST doesn't use it.  Attaching nvmem to iobus solves this issue.
         # During initialization, system_port -> membus -> iobus -> nvmem.
-        if external_memory:
+        if external_memory or ruby:
             self.realview.setupBootLoader(self.iobus,  self, binary)
         else:
             self.realview.setupBootLoader(self.membus, self, binary)
@@ -366,20 +367,31 @@ def makeArmSystem(mem_mode, machine_type, num_cpus=1, mdesc=None,
         self.bridge.ranges = [self.realview.nvmem.range]
 
         self.realview.attachOnChipIO(self.iobus)
+        # Attach off-chip devices
+        self.realview.attachIO(self.iobus)
+    elif ruby:
+        self._dma_ports = [ ]
+        self.realview.attachOnChipIO(self.iobus, dma_ports=self._dma_ports)
+        # Force Ruby to treat the boot ROM as an IO device.
+        self.realview.nvmem.in_addr_map = False
+        self.realview.attachIO(self.iobus, dma_ports=self._dma_ports)
     else:
         self.realview.attachOnChipIO(self.membus, self.bridge)
+        # Attach off-chip devices
+        self.realview.attachIO(self.iobus)
 
-    # Attach off-chip devices
-    self.realview.attachIO(self.iobus)
     for dev_id, dev in enumerate(pci_devices):
         dev.pci_bus, dev.pci_dev, dev.pci_func = (0, dev_id + 1, 0)
-        self.realview.attachPciDevice(dev, self.iobus)
+        self.realview.attachPciDevice(
+            dev, self.iobus,
+            dma_ports=self._dma_ports if ruby else None)
 
     self.intrctrl = IntrControl()
     self.terminal = Terminal()
     self.vncserver = VncServer()
 
-    self.system_port = self.membus.slave
+    if not ruby:
+        self.system_port = self.membus.slave
 
     return self
 
diff --git a/configs/example/fs.py b/configs/example/fs.py
index 6ee969a6e..a916ca49f 100644
--- a/configs/example/fs.py
+++ b/configs/example/fs.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2010-2013 ARM Limited
+# Copyright (c) 2010-2013, 2016 ARM Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -99,7 +99,8 @@ def build_test_system(np):
                                  options.num_cpus, bm[0], options.dtb_filename,
                                  bare_metal=options.bare_metal,
                                  cmdline=cmdline,
-                                 external_memory=options.external_memory_system)
+                                 external_memory=options.external_memory_system,
+                                 ruby=options.ruby)
         if options.enable_context_switch_stats_dump:
             test_sys.enable_context_switch_stats_dump = True
     else:
@@ -172,10 +173,11 @@ def build_test_system(np):
             cpu.icache_port = test_sys.ruby._cpu_ports[i].slave
             cpu.dcache_port = test_sys.ruby._cpu_ports[i].slave
 
-            if buildEnv['TARGET_ISA'] == "x86":
+            if buildEnv['TARGET_ISA'] in ("x86", "arm"):
                 cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave
                 cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave
 
+            if buildEnv['TARGET_ISA'] in "x86":
                 cpu.interrupts[0].pio = test_sys.ruby._cpu_ports[i].master
                 cpu.interrupts[0].int_master = test_sys.ruby._cpu_ports[i].slave
                 cpu.interrupts[0].int_slave = test_sys.ruby._cpu_ports[i].master