From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 7 Apr 2019 11:59:22 +0000 (+0100)
Subject: still transmit data if ready
X-Git-Tag: ls180-24jan2020~1300
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=eb894f6dfdbca627f87db573f78db5afedbed93c;p=ieee754fpu.git

still transmit data if ready
---

diff --git a/src/add/singlepipe.py b/src/add/singlepipe.py
index d7f0972d..248a5f6e 100644
--- a/src/add/singlepipe.py
+++ b/src/add/singlepipe.py
@@ -705,8 +705,9 @@ class BufferedPipeline2(ControlBase):
                                  ]
         # previous invalid or not ready, however next is accepting
         with self.m.Elif(n_i_ready):
+            self.m.d.sync += [ eq(self.n.o_data, result)]
             # TODO: could still send data here (if there was any)
-            self.m.d.sync += self.n.o_valid.eq(0), # ...so set output invalid
+            self.m.d.sync += self.n.o_valid.eq(0) # ...so set output invalid
 
         # if next is ready, so is previous
         self.m.d.comb += self.p._o_ready.eq(n_i_ready)