From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 2 Jun 2020 11:19:32 +0000 (+0100)
Subject: add MSR constants, TODO translated
X-Git-Tag: div_pipeline~658
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=eb92f0026544f4d77498c3b0020062171250939d;p=soc.git

add MSR constants, TODO translated
---

diff --git a/src/soc/fu/trap/main_stage.py b/src/soc/fu/trap/main_stage.py
index ff79d646..bbd00b64 100644
--- a/src/soc/fu/trap/main_stage.py
+++ b/src/soc/fu/trap/main_stage.py
@@ -14,6 +14,17 @@ from soc.decoder.power_enums import InternalOp
 from soc.decoder.power_fields import DecodeFields
 from soc.decoder.power_fieldsn import SignalBitRange
 
+# TODO at some point move these to their own module (for use elsewhere)
+"""
+    -- MSR bit numbers
+    constant MSR_SF  : integer := (63 - 0);     -- Sixty-Four bit mode
+    constant MSR_EE  : integer := (63 - 48);    -- External interrupt Enable
+    constant MSR_PR  : integer := (63 - 49);    -- PRoblem state
+    constant MSR_IR  : integer := (63 - 58);    -- Instruction Relocation
+    constant MSR_DR  : integer := (63 - 59);    -- Data Relocation
+    constant MSR_RI  : integer := (63 - 62);    -- Recoverable Interrupt
+    constant MSR_LE  : integer := (63 - 63);    -- Little Endian
+"""
 
 class TrapMainStage(PipeModBase):
     def __init__(self, pspec):