From: Florent Kermarrec Date: Mon, 17 Sep 2012 15:00:47 +0000 (+0200) Subject: new MigLa Class, simplify & clean up X-Git-Tag: 24jan2021_ls180~2575^2~134 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=eba6a2c7649329c43bfac90a20f8b0b7550f520a;p=litex.git new MigLa Class, simplify & clean up --- diff --git a/examples/de0_nano/client/test_MigIo.py b/examples/de0_nano/client/test_MigIo.py index c37229f7..64c8727c 100644 --- a/examples/de0_nano/client/test_MigIo.py +++ b/examples/de0_nano/client/test_MigIo.py @@ -25,11 +25,11 @@ record_size = 1024 csr = Uart2Spi(1,115200) # Csr Addr -MIGIO0_ADDR = 0x0000 +MIGIO_ADDR = 0x0000 # MigScope Configuration # migIo -migIo0 = migIo.MigIo(MIGIO0_ADDR, 8, "IO", csr) +migIo0 = migIo.MigIo(MIGIO_ADDR, 8, "IO", csr) def led_anim0(): for i in range(10): diff --git a/examples/de0_nano/client/test_MigLa.py b/examples/de0_nano/client/test_MigLa.py index d431ba14..0922d6fe 100644 --- a/examples/de0_nano/client/test_MigLa.py +++ b/examples/de0_nano/client/test_MigLa.py @@ -8,7 +8,7 @@ from migen.bank.description import * import sys sys.path.append("../../../") -from migScope import trigger, recorder, migIo +from migScope import trigger, recorder, migIo, migLa from migScope.tools.truthtable import * from migScope.tools.vcd import * import spi2Csr @@ -25,22 +25,21 @@ dat_width = 16 record_size = 4096 # Csr Addr -MIGIO0_ADDR = 0x0000 -TRIGGER_ADDR = 0x0200 -RECORDER_ADDR = 0x0400 +MIGIO_ADDR = 0x0000 +MIGLA_ADDR = 0x0200 -csr = Uart2Spi(1,115200) +csr = Uart2Spi(1,115200,debug=False) # MigScope Configuration # migIo -migIo0 = migIo.MigIo(MIGIO0_ADDR, 8, "IO",csr) +migIo0 = migIo.MigIo(MIGIO_ADDR, 8, "IO",csr) # Trigger term0 = trigger.Term(trig_width) -trigger0 = trigger.Trigger(TRIGGER_ADDR, trig_width, dat_width, [term0], csr) +trigger0 = trigger.Trigger(trig_width, [term0]) +recorder0 = recorder.Recorder(dat_width, record_size) -# Recorder -recorder0 = recorder.Recorder(RECORDER_ADDR, dat_width, record_size, csr) +migLa0 = migLa.MigLa(MIGLA_ADDR, trigger0, recorder0, csr) #============================================================================== # T E S T M I G L A @@ -53,19 +52,19 @@ def capture(): global recorder0 global dat_vcd sum_tt = gen_truth_table("term0") - trigger0.sum.write(sum_tt) - recorder0.reset() - recorder0.offset(0) - recorder0.arm() + migLa0.trig.sum.write(sum_tt) + migLa0.rec.reset() + migLa0.rec.offset(0) + migLa0.rec.arm() print("-Recorder [Armed]") print("-Waiting Trigger...", end = ' ') - while(not recorder0.is_done()): + while(not migLa0.rec.is_done()): time.sleep(0.1) print("[Done]") print("-Receiving Data...", end = ' ') sys.stdout.flush() - dat_vcd += recorder0.read(1024) + dat_vcd += migLa0.rec.read(1024) print("[Done]") print("Capturing Ramp..") diff --git a/examples/de0_nano/top.py b/examples/de0_nano/top.py index a4701031..3dd60b89 100644 --- a/examples/de0_nano/top.py +++ b/examples/de0_nano/top.py @@ -42,7 +42,7 @@ from migen.bank.description import * import sys sys.path.append("../../") -from migScope import trigger, recorder, migIo +from migScope import trigger, recorder, migIo, migLa import spi2Csr from timings import * @@ -68,8 +68,7 @@ record_size = 4096 # Csr Addr MIGIO_ADDR = 0x0000 -TRIGGER_ADDR = 0x0200 -RECORDER_ADDR = 0x0400 +MIGLA_ADDR = 0x0200 #============================================================================== # M I S C O P E E X A M P L E @@ -79,13 +78,12 @@ def get(): # migIo migIo0 = migIo.MigIo(MIGIO_ADDR, 8, "IO") - # Trigger + # migLa term0 = trigger.Term(trig_width) + trigger0 = trigger.Trigger(trig_width, [term0]) + recorder0 = recorder.Recorder(dat_width, record_size) - trigger0 = trigger.Trigger(TRIGGER_ADDR, trig_width, dat_width, [term0]) - - # Recorder - recorder0 = recorder.Recorder(RECORDER_ADDR, dat_width, record_size) + migLa0 = migLa.MigLa(MIGLA_ADDR, trigger0, recorder0) # Spi2Csr spi2csr0 = spi2Csr.Spi2Csr(16,8) @@ -94,8 +92,8 @@ def get(): csrcon0 = csr.Interconnect(spi2csr0.csr, [ migIo0.bank.interface, - trigger0.bank.interface, - recorder0.bank.interface + migLa0.trig.bank.interface, + migLa0.rec.bank.interface ]) comb = [] sync = [] @@ -146,19 +144,12 @@ def get(): comb += [led0.eq(migIo0.o[:8])] - # Dat / Trig Bus + # MigLa0 input comb += [ - trigger0.in_trig.eq(sig_gen), - trigger0.in_dat.eq(sig_gen) + migLa0.in_trig.eq(sig_gen), + migLa0.in_dat.eq(sig_gen) ] - # Trigger --> Recorder - comb += [ - recorder0.trig_dat.eq(trigger0.dat), - recorder0.trig_hit.eq(trigger0.hit) - ] - - # HouseKeeping cd_in = ClockDomain("in") in_rst_n = Signal() diff --git a/examples/de1/client/test_MigIo.py b/examples/de1/client/test_MigIo.py index c37229f7..64c8727c 100644 --- a/examples/de1/client/test_MigIo.py +++ b/examples/de1/client/test_MigIo.py @@ -25,11 +25,11 @@ record_size = 1024 csr = Uart2Spi(1,115200) # Csr Addr -MIGIO0_ADDR = 0x0000 +MIGIO_ADDR = 0x0000 # MigScope Configuration # migIo -migIo0 = migIo.MigIo(MIGIO0_ADDR, 8, "IO", csr) +migIo0 = migIo.MigIo(MIGIO_ADDR, 8, "IO", csr) def led_anim0(): for i in range(10): diff --git a/examples/de1/client/test_MigLa.py b/examples/de1/client/test_MigLa.py index d431ba14..0922d6fe 100644 --- a/examples/de1/client/test_MigLa.py +++ b/examples/de1/client/test_MigLa.py @@ -8,7 +8,7 @@ from migen.bank.description import * import sys sys.path.append("../../../") -from migScope import trigger, recorder, migIo +from migScope import trigger, recorder, migIo, migLa from migScope.tools.truthtable import * from migScope.tools.vcd import * import spi2Csr @@ -25,22 +25,21 @@ dat_width = 16 record_size = 4096 # Csr Addr -MIGIO0_ADDR = 0x0000 -TRIGGER_ADDR = 0x0200 -RECORDER_ADDR = 0x0400 +MIGIO_ADDR = 0x0000 +MIGLA_ADDR = 0x0200 -csr = Uart2Spi(1,115200) +csr = Uart2Spi(1,115200,debug=False) # MigScope Configuration # migIo -migIo0 = migIo.MigIo(MIGIO0_ADDR, 8, "IO",csr) +migIo0 = migIo.MigIo(MIGIO_ADDR, 8, "IO",csr) # Trigger term0 = trigger.Term(trig_width) -trigger0 = trigger.Trigger(TRIGGER_ADDR, trig_width, dat_width, [term0], csr) +trigger0 = trigger.Trigger(trig_width, [term0]) +recorder0 = recorder.Recorder(dat_width, record_size) -# Recorder -recorder0 = recorder.Recorder(RECORDER_ADDR, dat_width, record_size, csr) +migLa0 = migLa.MigLa(MIGLA_ADDR, trigger0, recorder0, csr) #============================================================================== # T E S T M I G L A @@ -53,19 +52,19 @@ def capture(): global recorder0 global dat_vcd sum_tt = gen_truth_table("term0") - trigger0.sum.write(sum_tt) - recorder0.reset() - recorder0.offset(0) - recorder0.arm() + migLa0.trig.sum.write(sum_tt) + migLa0.rec.reset() + migLa0.rec.offset(0) + migLa0.rec.arm() print("-Recorder [Armed]") print("-Waiting Trigger...", end = ' ') - while(not recorder0.is_done()): + while(not migLa0.rec.is_done()): time.sleep(0.1) print("[Done]") print("-Receiving Data...", end = ' ') sys.stdout.flush() - dat_vcd += recorder0.read(1024) + dat_vcd += migLa0.rec.read(1024) print("[Done]") print("Capturing Ramp..") diff --git a/examples/de1/client/test_MigLa.vcd b/examples/de1/client/test_MigLa.vcd index 60a2bb0f..9781a270 100644 --- a/examples/de1/client/test_MigLa.vcd +++ b/examples/de1/client/test_MigLa.vcd @@ -1,5 +1,5 @@ $date - 2012-09-16 01:27 + 2012-09-17 17:00 $end $version miscope VCD dump diff --git a/examples/de1/top.py b/examples/de1/top.py index 10d1fd93..f9c83abb 100644 --- a/examples/de1/top.py +++ b/examples/de1/top.py @@ -42,7 +42,7 @@ from migen.bank.description import * import sys sys.path.append("../../") -from migScope import trigger, recorder, migIo +from migScope import trigger, recorder, migIo, migLa import spi2Csr from timings import * @@ -68,8 +68,7 @@ record_size = 4096 # Csr Addr MIGIO_ADDR = 0x0000 -TRIGGER_ADDR = 0x0200 -RECORDER_ADDR = 0x0400 +MIGLA_ADDR = 0x0200 #============================================================================== # M I S C O P E E X A M P L E @@ -79,13 +78,12 @@ def get(): # migIo migIo0 = migIo.MigIo(MIGIO_ADDR, 8, "IO") - # Trigger + # migLa term0 = trigger.Term(trig_width) + trigger0 = trigger.Trigger(trig_width, [term0]) + recorder0 = recorder.Recorder(dat_width, record_size) - trigger0 = trigger.Trigger(TRIGGER_ADDR, trig_width, dat_width, [term0]) - - # Recorder - recorder0 = recorder.Recorder(RECORDER_ADDR, dat_width, record_size) + migLa0 = migLa.MigLa(MIGLA_ADDR, trigger0, recorder0) # Spi2Csr spi2csr0 = spi2Csr.Spi2Csr(16,8) @@ -94,8 +92,8 @@ def get(): csrcon0 = csr.Interconnect(spi2csr0.csr, [ migIo0.bank.interface, - trigger0.bank.interface, - recorder0.bank.interface + migLa0.trig.bank.interface, + migLa0.rec.bank.interface ]) comb = [] sync = [] @@ -149,19 +147,12 @@ def get(): sw0 = Signal(BV(8)) comb += [migIo0.i.eq(sw0)] - # Dat / Trig Bus + # MigLa0 input comb += [ - trigger0.in_trig.eq(sig_gen), - trigger0.in_dat.eq(sig_gen) + migLa0.in_trig.eq(sig_gen), + migLa0.in_dat.eq(sig_gen) ] - # Trigger --> Recorder - comb += [ - recorder0.trig_dat.eq(trigger0.dat), - recorder0.trig_hit.eq(trigger0.hit) - ] - - # HouseKeeping cd_in = ClockDomain("in") in_rst_n = Signal() diff --git a/migScope/migIo.py b/migScope/migIo.py index 72024d5b..fba310ad 100644 --- a/migScope/migIo.py +++ b/migScope/migIo.py @@ -5,6 +5,9 @@ from migen.bank.description import * class MigIo: + # + # Definition + # def __init__(self,address, width, mode = "IO", interface=None): self.address = address self.width = width @@ -20,14 +23,7 @@ class MigIo: self.oreg = description.RegisterField("o", self.width) self.oreg.field.r.name_override = "ouptuts" self.bank = csrgen.Bank([self.oreg, self.ireg], address=self.address) - - def write(self, data): - self.interface.write_n(self.address, data, self.width) - - def read(self): - r = self.interface.read_n(self.address + self.words, self.width) - return r - + def get_fragment(self): comb = [] if "I" in self.mode: @@ -35,3 +31,12 @@ class MigIo: if "O" in self.mode: comb += [self.o.eq(self.oreg.field.r)] return Fragment(comb=comb) + self.bank.get_fragment() + # + #Driver + # + def write(self, data): + self.interface.write_n(self.address, data, self.width) + + def read(self): + r = self.interface.read_n(self.address + self.words, self.width) + return r \ No newline at end of file diff --git a/migScope/migLa.py b/migScope/migLa.py new file mode 100644 index 00000000..93f305aa --- /dev/null +++ b/migScope/migLa.py @@ -0,0 +1,36 @@ +from migen.fhdl.structure import * +from migen.bus import csr +from migen.bank import description, csrgen +from migen.bank.description import * + +import sys +sys.path.append("../") + +from migScope import trigger, recorder + +class MigLa: + def __init__(self,address, trig, rec, interface=None): + self.address = address + self.trig = trig + self.rec = rec + self.interface = interface + + self.in_trig = Signal(BV(self.trig.trig_width)) + self.in_dat = Signal(BV(self.trig.trig_width)) + + self.trig.set_address(self.address) + self.rec.set_address(self.address + 0x0200) + + self.trig.set_interface(self.interface) + self.rec.set_interface(self.interface) + + def get_fragment(self): + comb = [] + comb += [ + self.trig.in_trig.eq(self.in_trig), + ] + comb += [ + self.rec.trig_dat.eq(self.in_dat), + self.rec.trig_hit.eq(self.trig.hit) + ] + return Fragment(comb=comb) \ No newline at end of file diff --git a/migScope/recorder.py b/migScope/recorder.py index 9304b94d..a8570c3b 100644 --- a/migScope/recorder.py +++ b/migScope/recorder.py @@ -5,6 +5,9 @@ from migen.bank.description import * from migen.corelogic.misc import optree class Storage: + # + # Definition + # def __init__(self, width, depth): self.width = width self.depth = depth @@ -71,6 +74,9 @@ class Storage: return Fragment(comb=comb, sync=sync, memories=memories) class Sequencer: + # + # Definition + # def __init__(self,depth): self.depth = depth self.depth_width = bits_for(self.depth) @@ -116,7 +122,10 @@ class Sequencer: return Fragment(comb=comb, sync=sync) class Recorder: - def __init__(self,address, width, depth, interface = None): + # + # Definition + # + def __init__(self, width, depth, address = 0x0000, interface = None): self.address = address self.width = width self.depth = depth @@ -137,42 +146,23 @@ class Recorder: self._get = RegisterField("get", reset=0) self._get_dat = RegisterField("get_dat", self.width, reset=1, access_bus=READ_ONLY, access_dev=WRITE_ONLY) - regs = [self._rst, self._arm, self._done, + self.regs = [self._rst, self._arm, self._done, self._size, self._offset, self._get, self._get_dat] - self.bank = csrgen.Bank(regs,address=self.address) + self.bank = csrgen.Bank(self.regs,address=self.address) # Trigger Interface self.trig_hit = Signal() self.trig_dat = Signal(BV(self.width)) - def reset(self): - self.interface.write(self.address + 0x00, 1) - self.interface.write(self.address + 0x00, 0) - - def arm(self): - self.interface.write(self.address + 0x01, 1) - self.interface.write(self.address + 0x01, 0) - - def is_done(self): - return self.interface.read(self.address + 0x02) == 1 - - def size(self, dat): - self.size = dat - self.interface.write_n(self.address + 0x03, dat, 16) - - def offset(self, dat): - self.interface.write_n(self.address + 0x05, dat, 16) + def set_address(self, address): + self.address = address + self.bank = csrgen.Bank(self.regs,address=self.address) + + def set_interface(self, interface): + self.interface = interface - def read(self, size): - r = [] - for i in range(size): - self.interface.write(self.address+7, 1) - self.interface.write(self.address+7, 0) - r.append(self.interface.read_n(self.address+8,self.width)) - return r - def get_fragment(self): comb = [] sync = [] @@ -212,3 +202,32 @@ class Recorder: return self.bank.get_fragment()+\ self.storage.get_fragment()+self.sequencer.get_fragment()+\ Fragment(comb=comb, sync=sync) + + # + #Driver + # + def reset(self): + self.interface.write(self.address + 0x00, 1) + self.interface.write(self.address + 0x00, 0) + + def arm(self): + self.interface.write(self.address + 0x01, 1) + self.interface.write(self.address + 0x01, 0) + + def is_done(self): + return self.interface.read(self.address + 0x02) == 1 + + def size(self, dat): + self.size = dat + self.interface.write_n(self.address + 0x03, dat, 16) + + def offset(self, dat): + self.interface.write_n(self.address + 0x05, dat, 16) + + def read(self, size): + r = [] + for i in range(size): + self.interface.write(self.address+7, 1) + self.interface.write(self.address+7, 0) + r.append(self.interface.read_n(self.address+8,self.width)) + return r diff --git a/migScope/trigger.py b/migScope/trigger.py index 388d588d..477fc926 100644 --- a/migScope/trigger.py +++ b/migScope/trigger.py @@ -5,6 +5,9 @@ from migen.bank.description import * from migen.corelogic.misc import optree class Term: + # + # Definition + # def __init__(self, width, pipe=False): self.width = width self.pipe = pipe @@ -18,10 +21,7 @@ class Term: self.i = Signal(BV(self.width)) self.t = Signal(BV(self.width)) self.o = Signal() - - def write(self, dat): - self.interface.write_n(self.reg_base, dat ,self.width) - + def get_fragment(self): frag = [ self.o.eq(self.i==self.t) @@ -35,8 +35,16 @@ class Term: comb = [] comb += [self.t.eq(reg.field.r[0*self.width:1*self.width])] return comb + # + #Driver + # + def write(self, dat): + self.interface.write_n(self.reg_base, dat ,self.width) class RangeDetector: + # + # Definition + # def __init__(self, width, pipe=False): self.width = width self.pipe = pipe @@ -52,12 +60,6 @@ class RangeDetector: self.high = Signal(BV(self.width)) self.o = Signal() - def write_low(self, dat): - self.interface.write_n(self.reg_base, dat ,self.width) - - def write_high(self, dat): - self.interface.write_n(self.reg_base + self.words, dat ,self.width) - def get_fragment(self): frag = [ self.o.eq((self.i >= self.low) & ((self.i <= self.high))) @@ -72,8 +74,19 @@ class RangeDetector: comb += [self.low.eq(reg.field.r[0*self.width:1*self.width])] comb += [self.low.eq(reg.field.r[1*self.width:2*self.width])] return comb + # + #Driver + # + def write_low(self, dat): + self.interface.write_n(self.reg_base, dat ,self.width) + + def write_high(self, dat): + self.interface.write_n(self.reg_base + self.words, dat ,self.width) class EdgeDetector: + # + # Definition + # def __init__(self, width, pipe=False, mode = "RFB"): self.width = width self.pipe = pipe @@ -97,22 +110,6 @@ class EdgeDetector: self.bo = Signal() self.o = Signal() - def write_r(self, dat): - self.interface.write_n(self.reg_base, dat ,self.width) - - def write_f(self, dat): - offset = 0 - if "R" in self.mode: - offset += self.words - self.interface.write_n(self.reg_base + offset, dat ,self.width) - - def write_b(self, dat): - if "R" in self.mode: - offset += self.words - if "F" in self.mode: - offset += self.words - self.interface.write_n(self.reg_base + offset, dat ,self.width) - def get_fragment(self): comb = [] sync = [] @@ -148,7 +145,7 @@ class EdgeDetector: comb += [self.o.eq(self.ro | self.fo | self.bo)] return Fragment(comb, sync) - + def connect_to_reg(self, reg): comb = [] i = 0 @@ -162,8 +159,30 @@ class EdgeDetector: comb += [self.b_mask.eq(reg.field.r[i*self.width:(i+1)*self.width])] i += 1 return comb + + # + #Driver + # + def write_r(self, dat): + self.interface.write_n(self.reg_base, dat ,self.width) + + def write_f(self, dat): + offset = 0 + if "R" in self.mode: + offset += self.words + self.interface.write_n(self.reg_base + offset, dat ,self.width) + + def write_b(self, dat): + if "R" in self.mode: + offset += self.words + if "F" in self.mode: + offset += self.words + self.interface.write_n(self.reg_base + offset, dat ,self.width) class Timer: + # + # Definition + # def __init__(self, width): self.width = width self.interface = None @@ -212,6 +231,9 @@ class Timer: return Fragment(comb, sync) class Sum: + # + # Definition + # def __init__(self,width=4,pipe=False): self.width = width self.pipe = pipe @@ -233,15 +255,6 @@ class Sum: self._mem = Memory(1, 2**self.width, self._lut_port, self._prog_port) - def write(self, truth_table): - for i in range(len(truth_table)): - val = truth_table[i] - we = 1<<17 - dat = val<<16 - addr = i - self.interface.write_n(self.reg_base, we + dat + addr,self.reg_size) - self.interface.write_n(self.reg_base, dat + addr, self.reg_size) - def get_fragment(self): comb = [] sync = [] @@ -260,21 +273,33 @@ class Sum: self.prog.eq(reg.field.r[17]) ] return comb + + # + #Driver + # + def write(self, truth_table): + for i in range(len(truth_table)): + val = truth_table[i] + we = 1<<17 + dat = val<<16 + addr = i + self.interface.write_n(self.reg_base, we + dat + addr,self.reg_size) + self.interface.write_n(self.reg_base, dat + addr, self.reg_size) class Trigger: - def __init__(self,address, trig_width, dat_width, ports, interface = None): + # + # Definition + # + def __init__(self, trig_width, ports, address = 0x0000, interface = None): self.address = address self.trig_width = trig_width - self.dat_width = dat_width self.ports = ports self.interface = interface self.sum = Sum(len(self.ports)) self.in_trig = Signal(BV(self.trig_width)) - self.in_dat = Signal(BV(self.dat_width)) self.hit = Signal() - self.dat = Signal(BV(self.dat_width)) # Update port reg_name for i in range(len(self.ports)): @@ -286,19 +311,28 @@ class Trigger: access_bus=WRITE_ONLY, access_dev=READ_ONLY)) self.sum_reg = RegisterField(self.sum.reg_name, self.sum.reg_size, reset=0, access_bus=WRITE_ONLY, access_dev=READ_ONLY) - regs = [] + self.regs = [] objects = self.__dict__ for object in sorted(objects): if "_reg" in object: - regs.append(objects[object]) - self.bank = csrgen.Bank(regs,address=self.address) + self.regs.append(objects[object]) + self.bank = csrgen.Bank(self.regs,address=self.address) # Update base addr + self.set_address(self.address) + + # Update interface + self.set_interface(self.interface) + + def set_address(self, address): + self.address = address + self.bank = csrgen.Bank(self.regs,address=self.address) for port in self.ports: port.reg_base = self.bank.get_base(port.reg_name) self.sum.reg_base = self.bank.get_base(self.sum.reg_name) - # Update interface + def set_interface(self, interface): + self.interface = interface for port in self.ports: port.interface = self.interface self.sum.interface = self.interface @@ -320,7 +354,6 @@ class Trigger: frag += self.sum.get_fragment() for port in self.ports: frag += port.get_fragment() - comb+= [self.dat.eq(self.in_dat)] #Connect Registers for port in self.ports: