From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 17 Aug 2019 07:40:34 +0000 (+0100)
Subject: a_enabled and b_enabled into signals
X-Git-Tag: ls180-24jan2020~518
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ebb9a0d98ec414b92aa32d4478627e4482c4d7ca;p=ieee754fpu.git

a_enabled and b_enabled into signals
---

diff --git a/src/ieee754/part_mul_add/multiply.py b/src/ieee754/part_mul_add/multiply.py
index aa4fafb6..bdbb28cc 100644
--- a/src/ieee754/part_mul_add/multiply.py
+++ b/src/ieee754/part_mul_add/multiply.py
@@ -570,10 +570,14 @@ class Mul8_16_32_64(Elaboratable):
             byte_width = 8 // len(parts)
             bit_width = 8 * byte_width
             for i in range(len(parts)):
-                b_enabled = parts[i] & self.a[(i + 1) * bit_width - 1] \
+                ae = parts[i] & self.a[(i + 1) * bit_width - 1] \
                     & self._a_signed[i * byte_width]
-                a_enabled = parts[i] & self.b[(i + 1) * bit_width - 1] \
+                be = parts[i] & self.b[(i + 1) * bit_width - 1] \
                     & self._b_signed[i * byte_width]
+                a_enabled = Signal(name="a_enabled_%d" % i, reset_less=True)
+                b_enabled = Signal(name="b_enabled_%d" % i, reset_less=True)
+                m.d.comb += a_enabled.eq(ae)
+                m.d.comb += b_enabled.eq(be)
 
                 # for 8-bit values: form a * 0xFF00 by using -a * 0x100, the
                 # negation operation is split into a bitwise not and a +1.