From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 3 Jun 2019 19:37:02 +0000 (-0700)
Subject: Fix `ifndef
X-Git-Tag: working-ls180~1208^2~213
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ebcc85b9b86267a25e9126aa3d82ef4a0bd9f6fd;p=yosys.git

Fix `ifndef
---

diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index cce03980d..c8450f8d1 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -246,8 +246,8 @@ module FDCE ((* abc_flop_q *) output reg Q, input C, CE, (* abc_flop_d *) input
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_CLR_INVERTED = 1'b0;
   initial Q <= INIT;
-  generate case ({|IS_C_INVERTED, |IS_CLR_INVERTED})
 `ifndef _ABC
+  generate case ({|IS_C_INVERTED, |IS_CLR_INVERTED})
     2'b00: always @(posedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
     2'b01: always @(posedge C, negedge CLR) if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
     2'b10: always @(negedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;