From: lkcl <lkcl@web>
Date: Wed, 15 Sep 2021 12:38:50 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~128
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ebcef140732b100ccc68c5a747902cb4e0486e8c;p=libreriscv.git

---

diff --git a/openpower/sv/cr_ops.mdwn b/openpower/sv/cr_ops.mdwn
index eadfec921..0a55c586e 100644
--- a/openpower/sv/cr_ops.mdwn
+++ b/openpower/sv/cr_ops.mdwn
@@ -29,8 +29,9 @@ are firmly out of scope for
 this section.
 
 * Examples of v3.0B instructions to which this section does
-  apply is `mfcr` (3 bit operands) and `crnor` and `cmpi`
-  (5 bit operands).
+  apply is
+  - `mfcr` (3 bit operands) and
+  - `crnor` and `cmpi` (5 bit operands).
 * Examples to which this section does **not** apply include
   `fadds.` and `subf.` which both produce arithmetic results
   (and a CR Field co-result).