From: lkcl <lkcl@web>
Date: Fri, 2 Jun 2023 17:39:21 +0000 (+0100)
Subject: (no commit message)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ebd8c4b2e8a3ec7379e003d6974747b9a86ecc00;p=libreriscv.git

---

diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn
index 9298ed998..16a3d9660 100644
--- a/openpower/sv/svp64.mdwn
+++ b/openpower/sv/svp64.mdwn
@@ -220,9 +220,9 @@ accumulator than the registers.
 Simple-V operates on an entirely different paradigm from traditional
 Vector ISAs: as a "Sub-Execution Context", where "Elements" are synonymous
 with Scalar instructions. With this in mind
-implementations must observe Strict **Element**-Level Execution Order[^svp64_eeo]
+implementations must observe Strict **Element**-Level Execution Order[[#svp64_eeo]]
 at all times.
-*Any* element is Interruptible and Architectural State may
+*Any* element is Interruptible, and Architectural State may
 be fully preserved and restored regardless of that same State.
 
 *Engineering note: implementations are permitted have higher latency to
@@ -232,7 +232,8 @@ is active).*
 Interrupts still only save `MSR` and `PC` in `SRR0` and `SRR1`
 but the full SVP64 Architectural State may be saved and
 restored through manual copying of `SVSTATE` (and the four
-REMAP SPRs if in use at the time)
+REMAP SPRs if in use at the time, which may be determined by
+`SVSTATE[32:46]` being non-zero).
 
 *Programmer's note: Trap Handlers (and any stack-based context save/restore)
 must avoid the use of SVP64 Prefixed instructions to perform the necessary