From: Xan Date: Wed, 25 Apr 2018 10:51:35 +0000 (+0100) Subject: (no commit message) X-Git-Tag: convert-csv-opcode-to-binary~5528 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ebd8cadc440e44f2ae0874e571dd543e15628784;p=libreriscv.git --- diff --git a/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn b/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn index a28f8cfe9..da038b714 100644 --- a/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn +++ b/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn @@ -7,7 +7,8 @@ The harmonised RVP register file is divided into a lower bank of Vector[INT8] an | Register | Andes ISA | Harmonised RVP ISA | | ------------------ | ------------------------- | ------------------- | | v0 | Hardwired zero | Hardwired zero | -| v1 | 32bit GPR or Vector[4xINT8 or 2xINT16] | Predicate masks | +| v1 | 32bit GPR or Vector[4xINT8 or 2xINT16] | Predicate mask | +| | | | | v2 | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[4xSINT8] | | v3 | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[4xSINT8] | | v4 | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[4xSINT8] | @@ -37,6 +38,7 @@ The harmonised RVP register file is divided into a lower bank of Vector[INT8] an | v27 | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[2xUINT16] | | v28 | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[2xUINT16] | | v29 | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[2xUINT16] | +| | | | | v30 | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[1xSINT32] | | v31 | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[1xSINT32] |