From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 14 Feb 2015 23:20:05 +0000 (+0100)
Subject: Smaller default parameters in $mem simlib model
X-Git-Tag: yosys-0.6~434
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ec05242c27754224c8dd5d8c60828a0b43ef8f4c;p=yosys.git

Smaller default parameters in $mem simlib model
---

diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index ee024051b..bc343c62d 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -1539,9 +1539,9 @@ endmodule
 module \$mem (RD_CLK, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA);
 
 parameter MEMID = "";
-parameter SIZE = 256;
+parameter SIZE = 4;
 parameter OFFSET = 0;
-parameter ABITS = 8;
+parameter ABITS = 2;
 parameter WIDTH = 8;
 parameter signed INIT = 1'bx;