From: Dmitry Selyutin Date: Fri, 2 Jun 2023 16:23:02 +0000 (+0300) Subject: pysvp64asm: integrate into insndb X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ec2cdd8d2bb373edb7e5db4b41338c801ed56d3a;p=openpower-isa.git pysvp64asm: integrate into insndb --- diff --git a/setup.py b/setup.py index 58a7ec32..304b2c95 100644 --- a/setup.py +++ b/setup.py @@ -82,7 +82,7 @@ setup( 'pyfnwriter=openpower.decoder.pseudo.pyfnwriter:pyfnwriter', 'sv_analysis=openpower.sv.sv_analysis:main', 'pypowersim=openpower.decoder.isa.pypowersim:run_simulation', - 'pysvp64asm=openpower.sv.trans.svp64:asm_process', + 'pysvp64asm=openpower.insndb.asm:main', 'pysvp64dis=openpower.sv.trans.pysvp64dis:main' ] } diff --git a/src/openpower/decoder/isa/test_caller_setvl.py b/src/openpower/decoder/isa/test_caller_setvl.py index 163a5afe..a0661aa1 100644 --- a/src/openpower/decoder/isa/test_caller_setvl.py +++ b/src/openpower/decoder/isa/test_caller_setvl.py @@ -6,7 +6,7 @@ from openpower.decoder.isa.caller import CRFields, SVP64State from openpower.decoder.isa.test_caller import run_tst from openpower.decoder.selectable_int import SelectableInt from openpower.simulator.program import Program -from openpower.sv.trans.svp64 import SVP64Asm +from openpower.insndb.asm import SVP64Asm class DecoderTestCase(FHDLTestCase): diff --git a/src/openpower/decoder/isa/test_caller_svindex.py b/src/openpower/decoder/isa/test_caller_svindex.py index e33ad652..2c479c2f 100644 --- a/src/openpower/decoder/isa/test_caller_svindex.py +++ b/src/openpower/decoder/isa/test_caller_svindex.py @@ -9,7 +9,7 @@ from openpower.decoder.isa.caller import SVP64State, set_masked_reg from openpower.decoder.isa.test_caller import run_tst from openpower.decoder.selectable_int import SelectableInt from openpower.simulator.program import Program -from openpower.sv.trans.svp64 import SVP64Asm +from openpower.insndb.asm import SVP64Asm class SVSTATETestCase(FHDLTestCase): diff --git a/src/openpower/decoder/isa/test_caller_svp64.py b/src/openpower/decoder/isa/test_caller_svp64.py index e5ef3f39..e38ba963 100644 --- a/src/openpower/decoder/isa/test_caller_svp64.py +++ b/src/openpower/decoder/isa/test_caller_svp64.py @@ -7,7 +7,7 @@ from openpower.decoder.isa.caller import SVP64State from openpower.decoder.isa.test_caller import run_tst from openpower.decoder.selectable_int import SelectableInt from openpower.simulator.program import Program -from openpower.sv.trans.svp64 import SVP64Asm +from openpower.insndb.asm import SVP64Asm class DecoderTestCase(FHDLTestCase): diff --git a/src/openpower/decoder/isa/test_caller_svp64_bc.py b/src/openpower/decoder/isa/test_caller_svp64_bc.py index 159f08a2..23ba3b00 100644 --- a/src/openpower/decoder/isa/test_caller_svp64_bc.py +++ b/src/openpower/decoder/isa/test_caller_svp64_bc.py @@ -7,7 +7,7 @@ from openpower.decoder.isa.caller import SVP64State from openpower.decoder.isa.test_caller import run_tst from openpower.decoder.selectable_int import SelectableInt from openpower.simulator.program import Program -from openpower.sv.trans.svp64 import SVP64Asm +from openpower.insndb.asm import SVP64Asm class DecoderTestCase(FHDLTestCase): diff --git a/src/openpower/decoder/isa/test_caller_svp64_chacha20.py b/src/openpower/decoder/isa/test_caller_svp64_chacha20.py index 11ea2a08..0a0feac1 100644 --- a/src/openpower/decoder/isa/test_caller_svp64_chacha20.py +++ b/src/openpower/decoder/isa/test_caller_svp64_chacha20.py @@ -9,7 +9,7 @@ from openpower.decoder.isa.caller import SVP64State, set_masked_reg from openpower.decoder.isa.test_caller import run_tst from openpower.decoder.selectable_int import SelectableInt from openpower.simulator.program import Program -from openpower.sv.trans.svp64 import SVP64Asm +from openpower.insndb.asm import SVP64Asm # originally from https://github.com/pts/chacha20 diff --git a/src/openpower/decoder/isa/test_caller_svp64_dct.py b/src/openpower/decoder/isa/test_caller_svp64_dct.py index 940724f9..581b3522 100644 --- a/src/openpower/decoder/isa/test_caller_svp64_dct.py +++ b/src/openpower/decoder/isa/test_caller_svp64_dct.py @@ -12,7 +12,7 @@ from openpower.decoder.isafunctions.double2single import ( ISACallerFnHelper_double2single) from openpower.decoder.selectable_int import SelectableInt from openpower.simulator.program import Program -from openpower.sv.trans.svp64 import SVP64Asm +from openpower.insndb.asm import SVP64Asm # really bad hack. need to access the DOUBLE2SINGLE function auto-generated # from pseudo-code. diff --git a/src/openpower/decoder/isa/test_caller_svp64_dd_ffirst.py b/src/openpower/decoder/isa/test_caller_svp64_dd_ffirst.py index c9e98e48..666db4d2 100644 --- a/src/openpower/decoder/isa/test_caller_svp64_dd_ffirst.py +++ b/src/openpower/decoder/isa/test_caller_svp64_dd_ffirst.py @@ -6,7 +6,7 @@ from openpower.decoder.isa.caller import SVP64State from openpower.decoder.isa.test_caller import run_tst from openpower.decoder.selectable_int import SelectableInt from openpower.simulator.program import Program -from openpower.sv.trans.svp64 import SVP64Asm +from openpower.insndb.asm import SVP64Asm class DecoderTestCase(FHDLTestCase): diff --git a/src/openpower/decoder/isa/test_caller_svp64_fft.py b/src/openpower/decoder/isa/test_caller_svp64_fft.py index fceb6b38..bc201c31 100644 --- a/src/openpower/decoder/isa/test_caller_svp64_fft.py +++ b/src/openpower/decoder/isa/test_caller_svp64_fft.py @@ -8,7 +8,7 @@ from openpower.decoder.isafunctions.double2single import ( ISACallerFnHelper_double2single) from openpower.decoder.selectable_int import SelectableInt from openpower.simulator.program import Program -from openpower.sv.trans.svp64 import SVP64Asm +from openpower.insndb.asm import SVP64Asm # really bad hack. need to access the DOUBLE2SINGLE function auto-generated # from pseudo-code. diff --git a/src/openpower/decoder/isa/test_caller_svp64_fp.py b/src/openpower/decoder/isa/test_caller_svp64_fp.py index 703e95ab..920b21ad 100644 --- a/src/openpower/decoder/isa/test_caller_svp64_fp.py +++ b/src/openpower/decoder/isa/test_caller_svp64_fp.py @@ -5,7 +5,7 @@ from openpower.decoder.isa.caller import SVP64State from openpower.decoder.isa.test_caller import run_tst from openpower.decoder.selectable_int import SelectableInt from openpower.simulator.program import Program -from openpower.sv.trans.svp64 import SVP64Asm +from openpower.insndb.asm import SVP64Asm class DecoderTestCase(FHDLTestCase): diff --git a/src/openpower/decoder/isa/test_caller_svp64_inssort.py b/src/openpower/decoder/isa/test_caller_svp64_inssort.py index 86e706bb..816bb40b 100644 --- a/src/openpower/decoder/isa/test_caller_svp64_inssort.py +++ b/src/openpower/decoder/isa/test_caller_svp64_inssort.py @@ -5,7 +5,7 @@ from openpower.decoder.isa.caller import SVP64State from openpower.decoder.isa.test_caller import run_tst from openpower.decoder.selectable_int import SelectableInt from openpower.simulator.program import Program -from openpower.sv.trans.svp64 import SVP64Asm +from openpower.insndb.asm import SVP64Asm def signcopy(x, y): diff --git a/src/openpower/decoder/isa/test_caller_svp64_ldst.py b/src/openpower/decoder/isa/test_caller_svp64_ldst.py index 8e37fce1..4ecf5347 100644 --- a/src/openpower/decoder/isa/test_caller_svp64_ldst.py +++ b/src/openpower/decoder/isa/test_caller_svp64_ldst.py @@ -8,7 +8,7 @@ from openpower.decoder.isa.remap_dct_yield import halfrev2, reverse_bits from openpower.decoder.isa.test_caller import run_tst from openpower.decoder.selectable_int import SelectableInt from openpower.simulator.program import Program -from openpower.sv.trans.svp64 import SVP64Asm +from openpower.insndb.asm import SVP64Asm def write_byte(mem, addr, val): diff --git a/src/openpower/decoder/isa/test_caller_svp64_mapreduce.py b/src/openpower/decoder/isa/test_caller_svp64_mapreduce.py index dbca7847..9d547ba9 100644 --- a/src/openpower/decoder/isa/test_caller_svp64_mapreduce.py +++ b/src/openpower/decoder/isa/test_caller_svp64_mapreduce.py @@ -6,7 +6,7 @@ from openpower.decoder.isa.caller import SVP64State from openpower.decoder.isa.test_caller import run_tst from openpower.decoder.selectable_int import SelectableInt from openpower.simulator.program import Program -from openpower.sv.trans.svp64 import SVP64Asm +from openpower.insndb.asm import SVP64Asm class DecoderTestCase(FHDLTestCase): diff --git a/src/openpower/decoder/isa/test_caller_svp64_matrix.py b/src/openpower/decoder/isa/test_caller_svp64_matrix.py index 0796e7c9..65e0e341 100644 --- a/src/openpower/decoder/isa/test_caller_svp64_matrix.py +++ b/src/openpower/decoder/isa/test_caller_svp64_matrix.py @@ -7,7 +7,7 @@ from openpower.decoder.helpers import fp64toselectable from openpower.decoder.isa.test_caller import run_tst from openpower.decoder.selectable_int import SelectableInt from openpower.simulator.program import Program -from openpower.sv.trans.svp64 import SVP64Asm +from openpower.insndb.asm import SVP64Asm class DecoderTestCase(FHDLTestCase): diff --git a/src/openpower/decoder/isa/test_caller_svp64_pack.py b/src/openpower/decoder/isa/test_caller_svp64_pack.py index e3edd216..0e83b9eb 100644 --- a/src/openpower/decoder/isa/test_caller_svp64_pack.py +++ b/src/openpower/decoder/isa/test_caller_svp64_pack.py @@ -5,7 +5,7 @@ from openpower.decoder.isa.caller import CRFields, SVP64State from openpower.decoder.isa.test_caller import run_tst from openpower.decoder.selectable_int import SelectableInt from openpower.simulator.program import Program -from openpower.sv.trans.svp64 import SVP64Asm +from openpower.insndb.asm import SVP64Asm class DecoderTestCase(FHDLTestCase): diff --git a/src/openpower/decoder/isa/test_caller_svp64_parallel_reduce.py b/src/openpower/decoder/isa/test_caller_svp64_parallel_reduce.py index 88004682..c6ea8beb 100644 --- a/src/openpower/decoder/isa/test_caller_svp64_parallel_reduce.py +++ b/src/openpower/decoder/isa/test_caller_svp64_parallel_reduce.py @@ -7,7 +7,7 @@ from openpower.decoder.isa.remap_preduce_yield import preduce_y from openpower.decoder.isa.test_caller import run_tst from openpower.decoder.selectable_int import SelectableInt from openpower.simulator.program import Program -from openpower.sv.trans.svp64 import SVP64Asm +from openpower.insndb.asm import SVP64Asm def signcopy(x, y): diff --git a/src/openpower/decoder/isa/test_caller_svp64_predication.py b/src/openpower/decoder/isa/test_caller_svp64_predication.py index a0552e75..0670abfb 100644 --- a/src/openpower/decoder/isa/test_caller_svp64_predication.py +++ b/src/openpower/decoder/isa/test_caller_svp64_predication.py @@ -6,7 +6,7 @@ from openpower.decoder.isa.caller import CRFields, SVP64State from openpower.decoder.isa.test_caller import run_tst from openpower.decoder.selectable_int import SelectableInt from openpower.simulator.program import Program -from openpower.sv.trans.svp64 import SVP64Asm +from openpower.insndb.asm import SVP64Asm class DecoderTestCase(FHDLTestCase): diff --git a/src/openpower/decoder/isa/test_caller_svp64_subvl.py b/src/openpower/decoder/isa/test_caller_svp64_subvl.py index 01f1232e..cfd254d2 100644 --- a/src/openpower/decoder/isa/test_caller_svp64_subvl.py +++ b/src/openpower/decoder/isa/test_caller_svp64_subvl.py @@ -6,7 +6,7 @@ from openpower.decoder.isa.caller import SVP64State from openpower.decoder.isa.test_caller import run_tst from openpower.decoder.selectable_int import SelectableInt from openpower.simulator.program import Program -from openpower.sv.trans.svp64 import SVP64Asm +from openpower.insndb.asm import SVP64Asm class DecoderTestCase(FHDLTestCase): diff --git a/src/openpower/decoder/isa/test_caller_svshape2.py b/src/openpower/decoder/isa/test_caller_svshape2.py index 53ae23c9..75aad211 100644 --- a/src/openpower/decoder/isa/test_caller_svshape2.py +++ b/src/openpower/decoder/isa/test_caller_svshape2.py @@ -9,7 +9,7 @@ from openpower.decoder.isa.caller import SVP64State from openpower.decoder.isa.test_caller import run_tst from openpower.decoder.selectable_int import SelectableInt from openpower.simulator.program import Program -from openpower.sv.trans.svp64 import SVP64Asm +from openpower.insndb.asm import SVP64Asm class SVSTATETestCase(FHDLTestCase): diff --git a/src/openpower/decoder/isa/test_caller_svstate.py b/src/openpower/decoder/isa/test_caller_svstate.py index c8ef62c3..48c4b6f2 100644 --- a/src/openpower/decoder/isa/test_caller_svstate.py +++ b/src/openpower/decoder/isa/test_caller_svstate.py @@ -8,7 +8,7 @@ from openpower.decoder.isa.caller import CRFields, SVP64State from openpower.decoder.isa.test_caller import run_tst from openpower.decoder.selectable_int import SelectableInt from openpower.simulator.program import Program -from openpower.sv.trans.svp64 import SVP64Asm +from openpower.insndb.asm import SVP64Asm class SVSTATETestCase(FHDLTestCase): diff --git a/src/openpower/decoder/isa/test_caller_transcendentals.py b/src/openpower/decoder/isa/test_caller_transcendentals.py index 6c6304f2..c61faa5d 100644 --- a/src/openpower/decoder/isa/test_caller_transcendentals.py +++ b/src/openpower/decoder/isa/test_caller_transcendentals.py @@ -8,7 +8,7 @@ from openpower.decoder.isafunctions.double2single import ( ISACallerFnHelper_double2single) from openpower.decoder.selectable_int import SelectableInt from openpower.simulator.program import Program -from openpower.sv.trans.svp64 import SVP64Asm +from openpower.insndb.asm import SVP64Asm # really bad hack. need to access the DOUBLE2SINGLE function auto-generated # from pseudo-code. diff --git a/src/openpower/insndb/asm.py b/src/openpower/insndb/asm.py new file mode 100644 index 00000000..8ed34b8d --- /dev/null +++ b/src/openpower/insndb/asm.py @@ -0,0 +1,321 @@ +# SPDX-License-Identifier: LGPLv3+ +# Copyright (C) 2021 Luke Kenneth Casson Leighton +# Funded by NLnet http://nlnet.nl + +"""SVP64 OpenPOWER v3.0B assembly translator + +This class takes raw svp64 assembly mnemonics (aliases excluded) and creates +an EXT001-encoded "svp64 prefix" (as a .long) followed by a v3.0B opcode. + +It is very simple and straightforward, the only weirdness being the +extraction of the register information and conversion to v3.0B numbering. + +Encoding format of svp64: https://libre-soc.org/openpower/sv/svp64/ +Encoding format of arithmetic: https://libre-soc.org/openpower/sv/normal/ +Encoding format of LDST: https://libre-soc.org/openpower/sv/ldst/ +**TODO format of branches: https://libre-soc.org/openpower/sv/branches/** +**TODO format of CRs: https://libre-soc.org/openpower/sv/cr_ops/** +Bugtracker: https://bugs.libre-soc.org/show_bug.cgi?id=578 +""" + +import functools +import os +import sys +from collections import OrderedDict +import inspect + +from openpower.decoder.pseudo.pagereader import ISA +from openpower.decoder.power_svp64 import SVP64RM, get_regtype, decode_extra +from openpower.decoder.selectable_int import SelectableInt +from openpower.consts import SVP64MODE +from openpower.insndb.types import SVP64Instruction +from openpower.insndb.types import Database +from openpower.insndb.types import Style +from openpower.insndb.types import WordInstruction +from openpower.decoder.power_enums import find_wiki_dir + +# for debug logging +from openpower.util import log + + +DB = Database(find_wiki_dir()) + + +class AssemblerError(ValueError): + pass + + +# decodes svp64 assembly listings and creates EXT001 svp64 prefixes +class SVP64Asm: + def __init__(self, lst, bigendian=False, macros=None): + if macros is None: + macros = {} + self.macros = macros + self.lst = lst + self.trans = self.translate(lst) + self.isa = ISA() # reads the v3.0B pseudo-code markdown files + self.svp64 = SVP64RM() # reads the svp64 Remap entries for registers + assert bigendian == False, "error, bigendian not supported yet" + + def __iter__(self): + yield from self.trans + + def translate_one(self, insn, macros=None): + if macros is None: + macros = {} + macros.update(self.macros) + isa = self.isa + svp64 = self.svp64 + insn_no_comments = insn.partition('#')[0].strip() + if not insn_no_comments: + return + + # find first space, to get opcode + ls = insn_no_comments.split() + opcode = ls[0] + # now find opcode fields + fields = ''.join(ls[1:]).split(',') + mfields = list(filter(bool, map(str.strip, fields))) + log("opcode, fields", ls, opcode, mfields) + fields = [] + # macro substitution + for field in mfields: + fields.append(macro_subst(macros, field)) + log("opcode, fields substed", ls, opcode, fields) + + # identify if it is a word instruction + record = DB[opcode] + if record is not None: + insn = WordInstruction.assemble(record=record, arguments=fields) + yield from insn.disassemble(record=record, style=Style.LEGACY) + return + + # identify if is a svp64 mnemonic + if not opcode.startswith('sv.'): + yield insn # unaltered + return + opcode = opcode[3:] # strip leading "sv" + + # start working on decoding the svp64 op: sv.basev30Bop/vec2/mode + opmodes = opcode.split("/") # split at "/" + v30b_op = opmodes.pop(0) # first is the v3.0B + + record = DB[v30b_op] + if record is not None: + insn = SVP64Instruction.assemble(record=record, + arguments=fields, specifiers=opmodes) + yield from insn.disassemble(record=record, style=Style.LEGACY) + return + + raise AssemblerError(insn_no_comments) + + def translate(self, lst): + for insn in lst: + yield from self.translate_one(insn) + + +def macro_subst(macros, txt): + again = True + log("subst", txt, macros) + while again: + again = False + for macro, value in macros.items(): + if macro == txt: + again = True + replaced = txt.replace(macro, value) + log("macro", txt, "replaced", replaced, macro, value) + txt = replaced + continue + toreplace = '%s.s' % macro + if toreplace == txt: + again = True + replaced = txt.replace(toreplace, "%s.s" % value) + log("macro", txt, "replaced", replaced, toreplace, value) + txt = replaced + continue + toreplace = '%s.v' % macro + if toreplace == txt: + again = True + replaced = txt.replace(toreplace, "%s.v" % value) + log("macro", txt, "replaced", replaced, toreplace, value) + txt = replaced + continue + toreplace = '*%s' % macro + if toreplace in txt: + again = True + replaced = txt.replace(toreplace, '*%s' % value) + log("macro", txt, "replaced", replaced, toreplace, value) + txt = replaced + continue + toreplace = '(%s)' % macro + if toreplace in txt: + again = True + replaced = txt.replace(toreplace, '(%s)' % value) + log("macro", txt, "replaced", replaced, toreplace, value) + txt = replaced + continue + log(" processed", txt) + return txt + + +def get_ws(line): + # find whitespace + ws = '' + while line: + if not line[0].isspace(): + break + ws += line[0] + line = line[1:] + return ws, line + + +def main(): + # get an input file and an output file + args = sys.argv[1:] + if len(args) == 0: + infile = sys.stdin + outfile = sys.stdout + # read the whole lot in advance in case of in-place + lines = list(infile.readlines()) + elif len(args) != 2: + print("pysvp64asm [infile | -] [outfile | -]", file=sys.stderr) + exit(0) + else: + if args[0] == '--': + infile = sys.stdin + else: + infile = open(args[0], "r") + # read the whole lot in advance in case of in-place overwrite + lines = list(infile.readlines()) + + if args[1] == '--': + outfile = sys.stdout + else: + outfile = open(args[1], "w") + + # read the line, look for custom insn, process it + macros = {} # macros which start ".set" + isa = SVP64Asm([]) + for line in lines: + op = line.split("#")[0].strip() + # identify macros + if op.startswith(".set"): + macro = op[4:].split(",") + (macro, value) = map(str.strip, macro) + macros[macro] = value + + if not op or op.startswith("#"): + outfile.write(line) + continue + (ws, line) = get_ws(line) + lst = isa.translate_one(op, macros) + lst = '; '.join(lst) + outfile.write("%s%s # %s\n" % (ws, lst, op)) + + +if __name__ == '__main__': + lst = ['slw 3, 1, 4', + 'extsw 5, 3', + 'sv.extsw 5, 3', + 'sv.cmpi 5, 1, 3, 2', + 'sv.setb 5, 31', + 'sv.isel 64.v, 3, 2, 65.v', + 'sv.setb/dm=r3/sm=1< -# Funded by NLnet http://nlnet.nl - -"""SVP64 OpenPOWER v3.0B assembly translator - -This class takes raw svp64 assembly mnemonics (aliases excluded) and creates -an EXT001-encoded "svp64 prefix" (as a .long) followed by a v3.0B opcode. - -It is very simple and straightforward, the only weirdness being the -extraction of the register information and conversion to v3.0B numbering. - -Encoding format of svp64: https://libre-soc.org/openpower/sv/svp64/ -Encoding format of arithmetic: https://libre-soc.org/openpower/sv/normal/ -Encoding format of LDST: https://libre-soc.org/openpower/sv/ldst/ -**TODO format of branches: https://libre-soc.org/openpower/sv/branches/** -**TODO format of CRs: https://libre-soc.org/openpower/sv/cr_ops/** -Bugtracker: https://bugs.libre-soc.org/show_bug.cgi?id=578 -""" - -import functools -import os -import sys -from collections import OrderedDict -import inspect - -from openpower.decoder.pseudo.pagereader import ISA -from openpower.decoder.power_svp64 import SVP64RM, get_regtype, decode_extra -from openpower.decoder.selectable_int import SelectableInt -from openpower.consts import SVP64MODE -from openpower.insndb.types import SVP64Instruction -from openpower.insndb.types import Database -from openpower.insndb.types import Style -from openpower.insndb.types import WordInstruction -from openpower.decoder.power_enums import find_wiki_dir - -# for debug logging -from openpower.util import log - - -DB = Database(find_wiki_dir()) - - -class AssemblerError(ValueError): - pass - - -# decodes svp64 assembly listings and creates EXT001 svp64 prefixes -class SVP64Asm: - def __init__(self, lst, bigendian=False, macros=None): - if macros is None: - macros = {} - self.macros = macros - self.lst = lst - self.trans = self.translate(lst) - self.isa = ISA() # reads the v3.0B pseudo-code markdown files - self.svp64 = SVP64RM() # reads the svp64 Remap entries for registers - assert bigendian == False, "error, bigendian not supported yet" - - def __iter__(self): - yield from self.trans - - def translate_one(self, insn, macros=None): - if macros is None: - macros = {} - macros.update(self.macros) - isa = self.isa - svp64 = self.svp64 - insn_no_comments = insn.partition('#')[0].strip() - if not insn_no_comments: - return - - # find first space, to get opcode - ls = insn_no_comments.split() - opcode = ls[0] - # now find opcode fields - fields = ''.join(ls[1:]).split(',') - mfields = list(filter(bool, map(str.strip, fields))) - log("opcode, fields", ls, opcode, mfields) - fields = [] - # macro substitution - for field in mfields: - fields.append(macro_subst(macros, field)) - log("opcode, fields substed", ls, opcode, fields) - - # identify if it is a word instruction - record = DB[opcode] - if record is not None: - insn = WordInstruction.assemble(record=record, arguments=fields) - yield from insn.disassemble(record=record, style=Style.LEGACY) - return - - # identify if is a svp64 mnemonic - if not opcode.startswith('sv.'): - yield insn # unaltered - return - opcode = opcode[3:] # strip leading "sv" - - # start working on decoding the svp64 op: sv.basev30Bop/vec2/mode - opmodes = opcode.split("/") # split at "/" - v30b_op = opmodes.pop(0) # first is the v3.0B - - record = DB[v30b_op] - if record is not None: - insn = SVP64Instruction.assemble(record=record, - arguments=fields, specifiers=opmodes) - yield from insn.disassemble(record=record, style=Style.LEGACY) - return - - raise AssemblerError(insn_no_comments) - - def translate(self, lst): - for insn in lst: - yield from self.translate_one(insn) - - -def macro_subst(macros, txt): - again = True - log("subst", txt, macros) - while again: - again = False - for macro, value in macros.items(): - if macro == txt: - again = True - replaced = txt.replace(macro, value) - log("macro", txt, "replaced", replaced, macro, value) - txt = replaced - continue - toreplace = '%s.s' % macro - if toreplace == txt: - again = True - replaced = txt.replace(toreplace, "%s.s" % value) - log("macro", txt, "replaced", replaced, toreplace, value) - txt = replaced - continue - toreplace = '%s.v' % macro - if toreplace == txt: - again = True - replaced = txt.replace(toreplace, "%s.v" % value) - log("macro", txt, "replaced", replaced, toreplace, value) - txt = replaced - continue - toreplace = '*%s' % macro - if toreplace in txt: - again = True - replaced = txt.replace(toreplace, '*%s' % value) - log("macro", txt, "replaced", replaced, toreplace, value) - txt = replaced - continue - toreplace = '(%s)' % macro - if toreplace in txt: - again = True - replaced = txt.replace(toreplace, '(%s)' % value) - log("macro", txt, "replaced", replaced, toreplace, value) - txt = replaced - continue - log(" processed", txt) - return txt - - -def get_ws(line): - # find whitespace - ws = '' - while line: - if not line[0].isspace(): - break - ws += line[0] - line = line[1:] - return ws, line - - -def asm_process(): - # get an input file and an output file - args = sys.argv[1:] - if len(args) == 0: - infile = sys.stdin - outfile = sys.stdout - # read the whole lot in advance in case of in-place - lines = list(infile.readlines()) - elif len(args) != 2: - print("pysvp64asm [infile | -] [outfile | -]", file=sys.stderr) - exit(0) - else: - if args[0] == '--': - infile = sys.stdin - else: - infile = open(args[0], "r") - # read the whole lot in advance in case of in-place overwrite - lines = list(infile.readlines()) - - if args[1] == '--': - outfile = sys.stdout - else: - outfile = open(args[1], "w") - - # read the line, look for custom insn, process it - macros = {} # macros which start ".set" - isa = SVP64Asm([]) - for line in lines: - op = line.split("#")[0].strip() - # identify macros - if op.startswith(".set"): - macro = op[4:].split(",") - (macro, value) = map(str.strip, macro) - macros[macro] = value - - if not op or op.startswith("#"): - outfile.write(line) - continue - (ws, line) = get_ws(line) - lst = isa.translate_one(op, macros) - lst = '; '.join(lst) - outfile.write("%s%s # %s\n" % (ws, lst, op)) - - -if __name__ == '__main__': - lst = ['slw 3, 1, 4', - 'extsw 5, 3', - 'sv.extsw 5, 3', - 'sv.cmpi 5, 1, 3, 2', - 'sv.setb 5, 31', - 'sv.isel 64.v, 3, 2, 65.v', - 'sv.setb/dm=r3/sm=1<