From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 4 Dec 2018 11:29:37 +0000 (+0000)
Subject: record conversation snippet
X-Git-Tag: convert-csv-opcode-to-binary~4811
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ec46c3a0b4287ab8acd370b1905bbac38608357d;p=libreriscv.git

record conversation snippet
---

diff --git a/3d_gpu/microarchitecture.mdwn b/3d_gpu/microarchitecture.mdwn
index 07576242a..f3e4f96d2 100644
--- a/3d_gpu/microarchitecture.mdwn
+++ b/3d_gpu/microarchitecture.mdwn
@@ -190,6 +190,20 @@ Reorder Buffer
     - Registers updated
     - Memory updated
 
+Reorder Buffer Entry
+
+* Instruction type
+    - branch (no destination resutl)
+    - store (has a memory address destination)
+    - register operation (ALU operation or load, which has reg dests)
+* Destination
+    - register number (for loads and ALU ops) or
+    - memory address (for stores) where the result should be written
+* Value
+    - value of instruction result, pending a commit
+* Ready
+    - indicates that the instruction has completed execution: value is ready
+
 # References
 
 * <https://en.wikipedia.org/wiki/Tomasulo_algorithm>