From: Luke Kenneth Casson Leighton Date: Tue, 27 Oct 2020 20:46:44 +0000 (+0000) Subject: further investigation note X-Git-Tag: convert-csv-opcode-to-binary~1910 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ec4c4e7df0ca649b0180883a32157e8c34c03b24;p=libreriscv.git further investigation note --- diff --git a/3d_gpu/architecture/compared_to_register_renaming.mdwn b/3d_gpu/architecture/compared_to_register_renaming.mdwn index 1e2866e34..9658de84b 100644 --- a/3d_gpu/architecture/compared_to_register_renaming.mdwn +++ b/3d_gpu/architecture/compared_to_register_renaming.mdwn @@ -56,7 +56,8 @@ f: Renamed hardware registers are named `h0`, `h1`, `h2`, ... -The syntax `ldu h7, 8(h5 -> h8)` will be used to mean that the address read comes from `h5` and the address write goes to `h8` +The syntax `ldu h7, 8(h5 -> h8)` will be used to mean that the address +read comes from `h5` and the address write goes to `h8` The register rename table starts out as following: