From: Michael Meissner Date: Thu, 30 Jun 2016 21:54:47 +0000 (+0000) Subject: re PR target/71677 (PowerPC ISA 3.0 DImode load/store needs a fix) X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ec5385270a31c82747239c962fdbb55a7b45ffde;p=gcc.git re PR target/71677 (PowerPC ISA 3.0 DImode load/store needs a fix) 2016-06-30 Michael Meissner PR target/71677 * config/rs6000/constraints.md (wY constraint): New constraint to match the requirements for the LXSD and STXSD instructions. * config/rs6000/predicates.md (offsettable_mem_14bit_operand): New predicate to match the requirements for the LXSD and STXSD instructions. * config/rs6000/rs6000.md (mov_hardfloat32, FMOVE64 case): Use constaint wY for LXSD/STXSD instructions instead of 'o' or 'Y' to make sure that the bottom 2 bits of offset are 0, the address form is offsettable, and no updating is done in the address mode. (mov_hardfloat64, FMOVE64 case): Likewise. (movdi_internal32): Likewise (movdi_internal64): Likewise. From-SVN: r237898 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 7bdcb074cba..bc39710bd24 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,19 @@ +2016-06-30 Michael Meissner + + PR target/71677 + * config/rs6000/constraints.md (wY constraint): New constraint to + match the requirements for the LXSD and STXSD instructions. + * config/rs6000/predicates.md (offsettable_mem_14bit_operand): New + predicate to match the requirements for the LXSD and STXSD + instructions. + * config/rs6000/rs6000.md (mov_hardfloat32, FMOVE64 case): + Use constaint wY for LXSD/STXSD instructions instead of 'o' or 'Y' + to make sure that the bottom 2 bits of offset are 0, the address + form is offsettable, and no updating is done in the address mode. + (mov_hardfloat64, FMOVE64 case): Likewise. + (movdi_internal32): Likewise + (movdi_internal64): Likewise. + 2016-06-30 Jakub Jelinek PR tree-optimization/71707 diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md index 8ef8f9b429e..18713256b9b 100644 --- a/gcc/config/rs6000/constraints.md +++ b/gcc/config/rs6000/constraints.md @@ -185,6 +185,11 @@ "Vector constant that can be loaded with XXSPLTIB & sign extension." (match_test "xxspltib_constant_split (op, mode)")) +;; ISA 3.0 D-form instruction that has the bottom 2 bits 0 (LXSD or STXSD). +(define_memory_constraint "wY" + "Offsettable memory operand, with bottom 2 bits 0" + (match_operand 0 "offsettable_mem_14bit_operand")) + ;; Altivec style load/store that ignores the bottom bits of the address (define_memory_constraint "wZ" "Indexed or indirect memory operand, ignoring the bottom 4 bits" diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md index 6436d5eb3a1..0d10e9ab5c1 100644 --- a/gcc/config/rs6000/predicates.md +++ b/gcc/config/rs6000/predicates.md @@ -734,6 +734,15 @@ (and (match_operand 0 "memory_operand") (match_test "offsettable_nonstrict_memref_p (op)"))) +;; Return 1 if the operand is an offsettable memory operand for ISA 3.0 +;; scalar LXSD/STXSD that must have the bottom 2 bits 0 and no update +;; form +(define_predicate "offsettable_mem_14bit_operand" + (and (match_operand 0 "memory_operand") + (match_test "offsettable_nonstrict_memref_p (op)") + (match_test "mem_operand_gpr (op, mode)") + (not (match_test "update_address_mem (op, mode)")))) + ;; Return 1 if the operand is suitable for load/store quad memory. ;; This predicate only checks for non-atomic loads/stores (not lqarx/stqcx). (define_predicate "quad_memory_operand" diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 81d189be166..a7615b1964b 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -6775,8 +6775,8 @@ ;; except for 0.0 which can be created on VSX with an xor instruction. (define_insn "*mov_hardfloat32" - [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,,Z,,o,,,!r,Y,r,!r") - (match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,,o,,,,,r,Y,r"))] + [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,,Z,,wY,,,!r,Y,r,!r") + (match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,,wY,,,,,r,Y,r"))] "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && (gpc_reg_operand (operands[0], mode) || gpc_reg_operand (operands[1], mode))" @@ -6814,8 +6814,8 @@ ; ld/std require word-aligned displacements -> 'Y' constraint. ; List Y->r and r->Y before r->r for reload. (define_insn "*mov_hardfloat64" - [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,,o,,Z,,,!r,Y,r,!r,*c*l,!r,*h,r,wg,r,") - (match_operand:FMOVE64 1 "input_operand" "d,m,d,o,,Z,,,,,r,Y,r,r,h,0,wg,r,,r"))] + [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,,wY,,Z,,,!r,Y,r,!r,*c*l,!r,*h,r,wg,r,") + (match_operand:FMOVE64 1 "input_operand" "d,m,d,wY,,Z,,,,,r,Y,r,r,h,0,wg,r,,r"))] "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && (gpc_reg_operand (operands[0], mode) || gpc_reg_operand (operands[1], mode))" @@ -7856,13 +7856,13 @@ (define_insn "*movdi_internal32" [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "=Y, r, r, ?m, ?*d, ?*d, - r, ?Y, ?Z, ?*wb, ?*wv, ?wi, + r, ?wY, ?Z, ?*wb, ?*wv, ?wi, ?wo, ?wo, ?wv, ?wi, ?wi, ?wv, ?wv") (match_operand:DI 1 "input_operand" "r, Y, r, d, m, d, - IJKnGHF, wb, wv, Y, Z, wi, + IJKnGHF, wb, wv, wY, Z, wi, Oj, wM, OjwM, Oj, wM, wS, wB"))] @@ -7932,14 +7932,14 @@ (define_insn "*movdi_internal64" [(set (match_operand:DI 0 "nonimmediate_operand" "=Y, r, r, r, r, r, - ?m, ?*d, ?*d, ?Y, ?Z, ?*wb, + ?m, ?*d, ?*d, ?wY, ?Z, ?*wb, ?*wv, ?wi, ?wo, ?wo, ?wv, ?wi, ?wi, ?wv, ?wv, r, *h, *h, ?*r, ?*wg, ?*r, ?*wj") (match_operand:DI 1 "input_operand" "r, Y, r, I, L, nF, - d, m, d, wb, wv, Y, + d, m, d, wb, wv, wY, Z, wi, Oj, wM, OjwM, Oj, wM, wS, wB, *h, r, 0, wg, r, wj, r"))]