From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Tue, 17 Mar 2015 11:11:51 +0000 (+0100)
Subject: liteeth: use CRG from Migen in base example
X-Git-Tag: 24jan2021_ls180~2483
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ec6ae750650a2a9adea7b284db1d9ef02e090826;p=litex.git

liteeth: use CRG from Migen in base example
---

diff --git a/misoclib/com/liteeth/example_designs/targets/base.py b/misoclib/com/liteeth/example_designs/targets/base.py
index 89afb297..ce27b063 100644
--- a/misoclib/com/liteeth/example_designs/targets/base.py
+++ b/misoclib/com/liteeth/example_designs/targets/base.py
@@ -1,5 +1,6 @@
 from migen.bus import wishbone
 from migen.bank.description import *
+from migen.genlib.io import CRG
 
 from misoclib.soc import SoC
 from misoclib.tools.litescope.common import *
@@ -12,20 +13,6 @@ from misoclib.com.liteeth.generic import *
 from misoclib.com.liteeth.phy.gmii import LiteEthPHYGMII
 from misoclib.com.liteeth.core import LiteEthUDPIPCore
 
-class _CRG(Module):
-	def __init__(self, clk_in):
-		self.clock_domains.cd_sys = ClockDomain()
-		self.clock_domains.cd_por = ClockDomain(reset_less=True)
-
-		# Power on Reset (vendor agnostic)
-		rst_n = Signal()
-		self.sync.por += rst_n.eq(1)
-		self.comb += [
-			self.cd_sys.clk.eq(clk_in),
-			self.cd_por.clk.eq(clk_in),
-			self.cd_sys.rst.eq(~rst_n)
-		]
-
 class BaseSoC(SoC, AutoCSR):
 	csr_map = {
 		"phy":		11,
@@ -44,8 +31,7 @@ class BaseSoC(SoC, AutoCSR):
 			with_identifier=True,
 			with_timer=False
 		)
-		clk_in = platform.request(platform.default_clk_name)
-		self.submodules.crg = _CRG(clk_in if not hasattr(clk_in, "p") else clk_in.p)
+		self.submodules.crg = CRG(platform.request(platform.default_clk_name))
 
 		# wishbone SRAM (to test Wishbone over UART and Etherbone)
 		self.submodules.sram = wishbone.SRAM(1024)