From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 16 Jul 2020 09:41:13 +0000 (+0100)
Subject: get trap compunit test working, adding bigendian and msr
X-Git-Tag: div_pipeline~9
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ec907fd9ebbfcd6574e9081600f4b4d64aa704c6;p=soc.git

get trap compunit test working, adding bigendian and msr
---

diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index f2ba7b28..ad4318ec 100644
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -598,10 +598,11 @@ class ISACaller:
             illegal = name != asmop
 
         if illegal:
-            print ("name %s != %s - calling ILLEGAL trap" % (name, asmop))
             self.TRAP(0x700, PI.ILLEG)
             self.namespace['NIA'] = self.trap_nia
             self.pc.update(self.namespace)
+            print ("name %s != %s - calling ILLEGAL trap, PC: %x" % \
+                    (name, asmop, self.pc.CIA.value))
             return
 
         info = self.instrs[name]
diff --git a/src/soc/fu/compunits/test/test_compunit.py b/src/soc/fu/compunits/test/test_compunit.py
index 7a73cb83..19358176 100644
--- a/src/soc/fu/compunits/test/test_compunit.py
+++ b/src/soc/fu/compunits/test/test_compunit.py
@@ -202,7 +202,7 @@ class TestRunner(FHDLTestCase):
                 instructions = list(zip(gen, insncode))
                 sim = ISA(simdec2, test.regs, test.sprs, test.cr, test.mem,
                           test.msr,
-                          initial_insns=gen, respect_pc=False,
+                          initial_insns=gen, respect_pc=True,
                           disassembly=insncode,
                           bigendian=self.bigendian)
 
@@ -211,7 +211,9 @@ class TestRunner(FHDLTestCase):
                     yield from setup_test_memory(l0, sim)
 
                 index = sim.pc.CIA.value//4
+                msr = sim.msr.value
                 while True:
+                    print("instr index", index)
                     try:
                         yield from sim.setup_one()
                     except KeyError: # indicates instruction not in imem: stop
@@ -222,6 +224,7 @@ class TestRunner(FHDLTestCase):
 
                     # ask the decoder to decode this binary data (endian'd)
                     yield pdecode2.dec.bigendian.eq(self.bigendian)  # le / be?
+                    yield pdecode2.msr.eq(msr)
                     yield instruction.eq(ins)          # raw binary instr.
                     yield Settle()
                     fn_unit = yield pdecode2.e.do.fn_unit
@@ -268,6 +271,7 @@ class TestRunner(FHDLTestCase):
                     yield from sim.execute_one()
                     yield Settle()
                     index = sim.pc.CIA.value//4
+                    msr = sim.msr.value
 
                     # get all outputs (one by one, just "because")
                     res = yield from get_cu_outputs(cu, code)
diff --git a/src/soc/fu/compunits/test/test_trap_compunit.py b/src/soc/fu/compunits/test/test_trap_compunit.py
index 86ea9478..7857b828 100644
--- a/src/soc/fu/compunits/test/test_trap_compunit.py
+++ b/src/soc/fu/compunits/test/test_trap_compunit.py
@@ -7,12 +7,12 @@ from soc.fu.trap.test.test_pipe_caller import TrapTestCase # creates the tests
 from soc.fu.test.common import ALUHelpers
 from soc.fu.compunits.compunits import TrapFunctionUnit
 from soc.fu.compunits.test.test_compunit import TestRunner
-
+from soc.config.endian import bigendian
 
 class TrapTestRunner(TestRunner):
     def __init__(self, test_data):
         super().__init__(test_data, TrapFunctionUnit, self,
-                         Function.TRAP)
+                         Function.TRAP, bigendian)
 
     def get_cu_inputs(self, dec2, sim):
         """naming (res) must conform to TrapFunctionUnit input regspec