From: Gabe Black <gblack@eecs.umich.edu>
Date: Sat, 7 Jan 2012 10:15:35 +0000 (-0800)
Subject: Merge with the main repository again.
X-Git-Tag: stable_2012_06_28~277
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ec936364b7238cddea7734ea79c6e04b52a683c6;p=gem5.git

Merge with the main repository again.
---

ec936364b7238cddea7734ea79c6e04b52a683c6
diff --cc src/cpu/BaseCPU.py
index b5c203742,665d42af0..50a8501e2
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@@ -167,15 -181,17 +167,16 @@@ class BaseCPU(MemObject)
          self.icache_port = ic.cpu_side
          self.dcache_port = dc.cpu_side
          self._cached_ports = ['icache.mem_side', 'dcache.mem_side']
-         if buildEnv['TARGET_ISA'] == 'x86' and iwc and dwc:
-             self.itb_walker_cache = iwc
-             self.dtb_walker_cache = dwc
-             self.itb.walker.port = iwc.cpu_side
-             self.dtb.walker.port = dwc.cpu_side
-             self._cached_ports += ["itb_walker_cache.mem_side", \
-                                    "dtb_walker_cache.mem_side"]
-         elif buildEnv['TARGET_ISA'] == 'arm':
-             self._cached_ports += ["itb.walker.port", "dtb.walker.port"]
 -        if buildEnv['FULL_SYSTEM']:
 -            if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
 -                if iwc and dwc:
 -                    self.itb_walker_cache = iwc
 -                    self.dtb_walker_cache = dwc
 -                    self.itb.walker.port = iwc.cpu_side
 -                    self.dtb.walker.port = dwc.cpu_side
 -                    self._cached_ports += ["itb_walker_cache.mem_side", \
 -                                           "dtb_walker_cache.mem_side"]
 -                else:
 -                    self._cached_ports += ["itb.walker.port", "dtb.walker.port"]
++        if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
++            if iwc and dwc:
++                self.itb_walker_cache = iwc
++                self.dtb_walker_cache = dwc
++                self.itb.walker.port = iwc.cpu_side
++                self.dtb.walker.port = dwc.cpu_side
++                self._cached_ports += ["itb_walker_cache.mem_side", \
++                                       "dtb_walker_cache.mem_side"]
++            else:
++                self._cached_ports += ["itb.walker.port", "dtb.walker.port"]
  
      def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None):
          self.addPrivateSplitL1Caches(ic, dc, iwc, dwc)