From: colepoirier <colepoirier@gmail.com>
Date: Wed, 27 May 2020 18:25:53 +0000 (-0700)
Subject: Fix indentation of regfile/formal/proof_regfile.py
X-Git-Tag: div_pipeline~783
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ec958b4107d55927b2c1f1d6fc48630b644410cd;p=soc.git

Fix indentation of regfile/formal/proof_regfile.py
---

diff --git a/src/soc/regfile/formal/proof_regfile.py b/src/soc/regfile/formal/proof_regfile.py
index 6ecad092..e37ea47d 100644
--- a/src/soc/regfile/formal/proof_regfile.py
+++ b/src/soc/regfile/formal/proof_regfile.py
@@ -8,7 +8,7 @@ from nmigen.test.utils import FHDLTestCase
 from nmigen.cli import rtlil
 import unittest
 
-from soc.regfile import Register
+from soc.regfile.regfile import Register
 
 
 class Driver(Elaboratable):
@@ -44,17 +44,17 @@ class Driver(Elaboratable):
         return m
 
 
-    def TestCase(FHDLTestCase):
-        def test_formal(self):
-            module = Driver()
-            self.assertFormal(module, mode="bmc", depth=2)
-            self.assertFormal(module, mode="cover", depth=2)
+class TestCase(FHDLTestCase):
+    def test_formal(self):
+        module = Driver()
+        self.assertFormal(module, mode="bmc", depth=2)
+        self.assertFormal(module, mode="cover", depth=2)
 
-        def test_ilang(self):
-            dut = Driver()
-            vl = rtlil.convert(dut, ports=[])
-            with open("regfile.il", "w") as f:
-                f.write(vl)
+    def test_ilang(self):
+        dut = Driver()
+        vl = rtlil.convert(dut, ports=[])
+        with open("regfile.il", "w") as f:
+            f.write(vl)
 
 
 if __name__ == '__main__':