From: lkcl <lkcl@web>
Date: Thu, 8 Sep 2022 17:08:15 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~598
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ec966bc691a69349775240c50a69a7d608b4f1cc;p=libreriscv.git

---

diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn
index f02126c24..7c40905df 100644
--- a/openpower/sv/rfc/ls001.mdwn
+++ b/openpower/sv/rfc/ls001.mdwn
@@ -200,6 +200,8 @@ Note critically that:
   then Vectorise because this creates the situation of Prefixed-Prefixed,
   resulting in deep complexity in Hardware Decode at a critical juncture, as
   well as introducing 96-bit instructions.
+* **All* of these Scalar instructions are candidates for Vectorisation.
+  Thus none of them may be 64-bit-Scalar-only.
 
 *Three 75% allocations are thus genuinely needed*, all other options are unsuitable
 for consideration.