From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 18 Mar 2020 13:59:48 +0000 (+0000)
Subject: done, http://bugs.libre-riscv.org/show_bug.cgi?id=261
X-Git-Tag: div_pipeline~1686
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ec9ecc1ec9142734821e15d963921557e80400e8;p=soc.git

done, bugs.libre-riscv.org/show_bug.cgi?id=261
---

diff --git a/src/soc/decoder/power_enums.py b/src/soc/decoder/power_enums.py
index cfa0bacb..fa7d1cab 100644
--- a/src/soc/decoder/power_enums.py
+++ b/src/soc/decoder/power_enums.py
@@ -217,7 +217,6 @@ class CryIn(Enum):
 
 # SPRs - Special-Purpose Registers.  See V3.0B Figure 18 p971 and
 # http://libre-riscv.org/openpower/isatables/sprs.csv
-# TODO: make this read the sprs.csv file
 # http://bugs.libre-riscv.org/show_bug.cgi?id=261
 
 spr_csv = get_csv("sprs.csv")