From: Paul Mackerras <paulus@ozlabs.org>
Date: Fri, 15 May 2020 12:01:02 +0000 (+1000)
Subject: dcache: Fix bug in store hit after dcbz case
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=eca0fb5bf1950043c4f424fd2dfc4f64694a728b;p=microwatt.git

dcache: Fix bug in store hit after dcbz case

This fixes a bug where a store that hits in the dcache immediately
following a dcbz has its write to the cache RAM suppressed (but not
its write to memory).  If a load to the same location comes along
before the cache line gets replaced, the load will return incorrect
data.

Fixes: 4db1676ef8b3 ("dcache: Don't assert on dcbz cache hit")
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
---

diff --git a/dcache.vhdl b/dcache.vhdl
index a9b5c4a..1d9cbda 100644
--- a/dcache.vhdl
+++ b/dcache.vhdl
@@ -980,7 +980,7 @@ begin
 		do_write <= '1';
 	    end if;
 	    if req_op = OP_STORE_HIT and req_hit_way = i and cancel_store = '0' and
-                r1.req.dcbz = '0' then
+                r0.req.dcbz = '0' then
 		assert not reloading report "Store hit while in state:" &
 		    state_t'image(r1.state)
 		    severity FAILURE;