From: lkcl <lkcl@web>
Date: Sun, 24 Apr 2022 21:32:25 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2601
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=eca3f05849a7983a77e8b7b186af9b2fa9067e3c;p=libreriscv.git

---

diff --git a/openpower/sv/biginteger/analysis.mdwn b/openpower/sv/biginteger/analysis.mdwn
index 1f422337c..5b56081de 100644
--- a/openpower/sv/biginteger/analysis.mdwn
+++ b/openpower/sv/biginteger/analysis.mdwn
@@ -390,3 +390,13 @@ puts the modulo back in as the hi-half of a 128/64-bit divide.
 By a nice coincidence this is exactly the same 128/64-bit operation
 needed for the `qhat` estimate if it may produce both the quotient and
 the remainder.
+
+`divrem2du RT,RA,RB,RC`
+
+     divisor = (RC) || (RB)
+     dividend = EXTZ128(RA) 
+     RT = UDIV(dividend, divisor)
+     RS = UREM(dividend, divisor)
+
+Again, using EXTRA mode bit 8 allows for selecting whether RS=RC or
+RS=RT+VL.