From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 9 Mar 2020 16:28:45 +0000 (+0000)
Subject: connect up LD to memory: set transparent mode to False.
X-Git-Tag: div_pipeline~1738
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=eca80986a909280f7ebce025c32040cc440d2e3c;p=soc.git

connect up LD to memory: set transparent mode to False.
need to check if the memory is valid one clock later
---

diff --git a/src/soc/experiment/compldst.py b/src/soc/experiment/compldst.py
index f9458cdf..853e2c80 100644
--- a/src/soc/experiment/compldst.py
+++ b/src/soc/experiment/compldst.py
@@ -253,6 +253,7 @@ class LDSTCompUnit(Elaboratable):
                 m.d.comb += self.alu.p_valid_i.eq(1) # so indicate valid
 
         # put the register directly onto the output bus on a go_write
+        # this is "ALU mode".  go_wr_i *must* be deasserted on next clock
         with m.If(self.go_wr_i):
             comb += self.data_o.eq(data_r)
 
@@ -260,14 +261,24 @@ class LDSTCompUnit(Elaboratable):
         with m.If(self.go_ad_i):
             comb += self.addr_o.eq(data_r)
 
-        # TODO: think about moving this to another module
-        # connect ST to memory
+        # TODO: think about moving these to another module
+
+        # connect ST to memory.  NOTE: unit *must* be set back
+        # to start again by dropping go_st_i on next clock
         with m.If(self.stwd_mem_o):
             wrport = self.mem.wrport
             comb += wrport.addr.eq(self.addr_o)
             comb += wrport.data.eq(src2_r)
             comb += wrport.en.eq(1)
 
+        # connect LD to memory.  NOTE: unit *must* be set back
+        # to start again by dropping go_ad_i on next clock
+        with m.If(self.load_mem_o):
+            rdport = self.mem.rdport
+            comb += rdport.addr.eq(self.addr_o)
+            comb += self.data_o.eq(rdport.data)
+            comb += rdport.en.eq(1)
+
         return m
 
     def __iter__(self):
diff --git a/src/soc/experiment/testmem.py b/src/soc/experiment/testmem.py
index 848bab7b..72b1a283 100644
--- a/src/soc/experiment/testmem.py
+++ b/src/soc/experiment/testmem.py
@@ -6,7 +6,7 @@ class TestMemory(Elaboratable):
         self.ddepth = 1 # regwid //8
         depth = (1<<addrw) // self.ddepth
         self.mem   = Memory(width=regwid, depth=depth, init=range(0, depth))
-        self.rdport = self.mem.read_port()
+        self.rdport = self.mem.read_port(transparent=False)
         self.wrport = self.mem.write_port()
 
     def elaborate(self, platform):