From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 4 May 2020 17:22:05 +0000 (-0700)
Subject: verilog: set src attribute for primitives
X-Git-Tag: working-ls180~571^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=eca9fc01a78c5cc4c1d8120e2ccdf18211bcef37;p=yosys.git

verilog: set src attribute for primitives
---

diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index 837c14ad7..488681649 100644
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -1739,8 +1739,10 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 
 			AstNode *node = children_list[1];
 			if (op_type != AST_POS)
-				for (size_t i = 2; i < children_list.size(); i++)
+				for (size_t i = 2; i < children_list.size(); i++) {
 					node = new AstNode(op_type, node, children_list[i]);
+					node->location = location;
+				}
 			if (invert_results)
 				node = new AstNode(AST_BIT_NOT, node);
 
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 4a5aba79e..f2ff685e9 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -1747,7 +1747,9 @@ single_prim:
 	/* no name */ {
 		astbuf2 = astbuf1->clone();
 		ast_stack.back()->children.push_back(astbuf2);
-	} '(' cell_port_list ')';
+	} '(' cell_port_list ')' {
+		SET_AST_NODE_LOC(astbuf2, @1, @$);
+	}
 
 cell_parameter_list_opt:
 	'#' '(' cell_parameter_list ')' | /* empty */;