From: Luke Kenneth Casson Leighton Date: Wed, 19 Jun 2019 14:58:04 +0000 (+0100) Subject: add SV VLIW idea X-Git-Tag: convert-csv-opcode-to-binary~4598 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ecb6f074bb84ad6eeccf3d455a408f05062bbbf4;p=libreriscv.git add SV VLIW idea --- diff --git a/simple_v_extension/specification.mdwn b/simple_v_extension/specification.mdwn index 44a6b8213..8f6c98bf1 100644 --- a/simple_v_extension/specification.mdwn +++ b/simple_v_extension/specification.mdwn @@ -2230,9 +2230,8 @@ Optional VL/MAXVL/SubVL Block: Reminder of the variable-length format from Section 1.5 of the RISC-V ISA: -| - | ---- | ---------------- | ---------------- | -------------------------- | | .. | xxxx | xxxxxxxxxxxxxxxx | xnnnxxxxx1111111 | (80+16\*nnn)-bit, nnn!=111 | -| - | ---- | ---------------- | ---------------- | -------------------------- | +| -- | ---- | ---------------- | ---------------- | -------------------------- | Notes: