From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Date: Tue, 12 May 2020 11:31:23 +0000 (+1000)
Subject: soc: Don't update CSR alignment when there is no CPU
X-Git-Tag: 24jan2021_ls180~353^2~2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ecbd40284a0c1d56c95cc1c13886847549365f2b;p=litex.git

soc: Don't update CSR alignment when there is no CPU

The alignment specified by the standalone core config should
be honored.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---

diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index 55bedb62..651f450d 100644
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -781,7 +781,13 @@ class SoC(Module):
         for n, (origin, size) in enumerate(self.cpu.io_regions.items()):
             self.bus.add_region("io{}".format(n), SoCIORegion(origin=origin, size=size, cached=False))
         self.mem_map.update(self.cpu.mem_map) # FIXME
-        self.csr.update_alignment(self.cpu.data_width)
+
+        # We don't want the CSR alignemnt reduced from 64-bit to 32-bit on
+        # a standalone system with a 64-bit WB and no CPU.
+        # Should we instead only update alignment if the CPU is *bigger*
+        # than the CSR ?
+        if name != "None":
+            self.csr.update_alignment(self.cpu.data_width)
         # Add Bus Masters/CSR/IRQs
         if not isinstance(self.cpu, cpu.CPUNone):
             if reset_address is None: