From: Ulrich Weigand Date: Tue, 29 Jan 2002 18:45:53 +0000 (+0000) Subject: s390.md (movstrsico, [...]): Remove, replace by ... X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ecbe845e2db207fa1f25ad71e9b67a0f60454929;p=gcc.git s390.md (movstrsico, [...]): Remove, replace by ... * config/s390/s390.md (movstrsico, movstrdix_64, movstrsix_31): Remove, replace by ... (movstrdi_short, movstrsi_short, movstrdi_long, movstrsi_long): ... these. New. (movstrdi, movstrsi): Adapt. (rotldi3, rotlsi3, ashldi3, *ashldi3_31, *ashldi3_64, ashlsi3, lshrdi3, *lshrdi3_31, *lshrdi3_64, lshrsi3): Remove unnecessary CC clobber. (*ashrdi3_cc_31, *ashrdi3_cconly_31, *ashrdi3_cc_64, *ashrdi3_cconly_64, *ashrsi3_cc, *ashrsi3_cconly): New. (divmoddi4): Don't partially initialize TImode register. From-SVN: r49325 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index b9fdd0d3567..86f65a30403 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,19 @@ +2002-01-29 Ulrich Weigand + + * config/s390/s390.md (movstrsico, movstrdix_64, + movstrsix_31): Remove, replace by ... + (movstrdi_short, movstrsi_short, movstrdi_long, + movstrsi_long): ... these. New. + (movstrdi, movstrsi): Adapt. + + (rotldi3, rotlsi3, ashldi3, *ashldi3_31, *ashldi3_64, + ashlsi3, lshrdi3, *lshrdi3_31, *lshrdi3_64, lshrsi3): + Remove unnecessary CC clobber. + (*ashrdi3_cc_31, *ashrdi3_cconly_31, *ashrdi3_cc_64, + *ashrdi3_cconly_64, *ashrsi3_cc, *ashrsi3_cconly): New. + + (divmoddi4): Don't partially initialize TImode register. + 2002-01-29 Geoffrey Keating * doc/sourcebuild.texi (C Tests): Document gcc.dg/debug directory. diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md index 9a50992f953..0208effa85c 100644 --- a/gcc/config/s390/s390.md +++ b/gcc/config/s390/s390.md @@ -1580,7 +1580,7 @@ operands[1] = change_address (operands[1], VOIDmode, addr1); operands[2] = GEN_INT (INTVAL (operands[2]) - 1); - emit_insn (gen_movstrsico (operands[0], operands[1], operands[2])); + emit_insn (gen_movstrdi_short (operands[0], operands[1], operands[2])); DONE; } else @@ -1609,21 +1609,30 @@ } else { - rtx label = gen_label_rtx (); - rtx reg0, reg1, len; + rtx label1 = gen_label_rtx (); + rtx label2 = gen_label_rtx (); + rtx reg0, reg1, len, blocks; reg0 = gen_reg_rtx (DImode); reg1 = gen_reg_rtx (DImode); len = gen_reg_rtx (DImode); + blocks = gen_reg_rtx (DImode); emit_move_insn (len, operands[2]); emit_insn (gen_cmpdi (len, const0_rtx)); - emit_jump_insn (gen_beq (label)); + emit_jump_insn (gen_beq (label1)); emit_move_insn (reg0, addr0); emit_move_insn (reg1, addr1); emit_insn (gen_adddi3 (len, len, constm1_rtx)); - emit_insn (gen_movstrdix_64 (reg0, reg1, reg0, reg1, len)); - emit_label (label); + emit_insn (gen_ashrdi3 (blocks, len, GEN_INT (8))); + emit_insn (gen_cmpdi (blocks, const0_rtx)); + emit_jump_insn (gen_beq (label2)); + emit_insn (gen_movstrdi_long (reg0, reg1, reg0, reg1, blocks, blocks)); + emit_label (label2); + operands[0] = change_address (operands[0], VOIDmode, reg0); + operands[1] = change_address (operands[1], VOIDmode, reg1); + emit_insn (gen_movstrdi_short (operands[0], operands[1], len)); + emit_label (label1); DONE; } } @@ -1638,7 +1647,7 @@ (match_operand:BLK 1 "general_operand" "")) (use (match_operand:SI 2 "general_operand" "")) (match_operand 3 "" "")] - "" + "!TARGET_64BIT" " { rtx addr0 = force_operand (XEXP (operands[0], 0), NULL_RTX); @@ -1650,14 +1659,11 @@ operands[1] = change_address (operands[1], VOIDmode, addr1); operands[2] = GEN_INT (INTVAL (operands[2]) - 1); - emit_insn (gen_movstrsico (operands[0], operands[1], operands[2])); + emit_insn (gen_movstrsi_short (operands[0], operands[1], operands[2])); DONE; } else { - if (TARGET_64BIT) - FAIL; - if (TARGET_MVCLE) { /* implementation suggested by Richard Henderson */ @@ -1683,119 +1689,141 @@ } else { - rtx label = gen_label_rtx (); - rtx reg0, reg1, len; + rtx label1 = gen_label_rtx (); + rtx label2 = gen_label_rtx (); + rtx reg0, reg1, len, blocks; reg0 = gen_reg_rtx (SImode); reg1 = gen_reg_rtx (SImode); len = gen_reg_rtx (SImode); + blocks = gen_reg_rtx (SImode); emit_move_insn (len, operands[2]); emit_insn (gen_cmpsi (len, const0_rtx)); - emit_jump_insn (gen_beq (label)); + emit_jump_insn (gen_beq (label1)); emit_move_insn (reg0, addr0); emit_move_insn (reg1, addr1); emit_insn (gen_addsi3 (len, len, constm1_rtx)); - emit_insn (gen_movstrsix_31 (reg0, reg1, reg0, reg1, len)); - emit_label (label); + emit_insn (gen_ashrsi3 (blocks, len, GEN_INT (8))); + emit_insn (gen_cmpsi (blocks, const0_rtx)); + emit_jump_insn (gen_beq (label2)); + emit_insn (gen_movstrsi_long (reg0, reg1, reg0, reg1, blocks, blocks)); + emit_label (label2); + operands[0] = change_address (operands[0], VOIDmode, reg0); + operands[1] = change_address (operands[1], VOIDmode, reg1); + emit_insn (gen_movstrsi_short (operands[0], operands[1], len)); + emit_label (label1); DONE; } } }") -; Move a block that is less than 256 bytes in length. +; Move a block that is up to 256 bytes in length. +; The block length is taken as (operands[2] % 256) + 1. -(define_insn "movstrsico" - [(set (match_operand:BLK 0 "s_operand" "=oQ") - (match_operand:BLK 1 "s_operand" "oQ")) - (use (match_operand 2 "const_int_operand" "I"))] - "((unsigned) INTVAL (operands[2]) < 256)" - "mvc\\t%O0(%c2+1,%R0),%1" - [(set_attr "op_type" "SS") - (set_attr "atype" "mem")]) +(define_insn "movstrdi_short" + [(set (match_operand:BLK 0 "s_operand" "=oQ,oQ") + (match_operand:BLK 1 "s_operand" "oQ,oQ")) + (use (match_operand:DI 2 "nonmemory_operand" "n,a")) + (clobber (match_scratch:DI 3 "=X,&a"))] + "TARGET_64BIT" + "* +{ + switch (which_alternative) + { + case 0: + return \"mvc\\t%O0(%b2+1,%R0),%1\"; + + case 1: + output_asm_insn (\"bras\\t%3,.+10\", operands); + output_asm_insn (\"mvc\\t%O0(1,%R0),%1\", operands); + return \"ex\\t%2,0(%3)\"; + + default: + abort (); + } +}" + [(set_attr "op_type" "SS,NN") + (set_attr "atype" "mem,mem") + (set_attr "length" "*,14")]) + +(define_insn "movstrsi_short" + [(set (match_operand:BLK 0 "s_operand" "=oQ,oQ") + (match_operand:BLK 1 "s_operand" "oQ,oQ")) + (use (match_operand:SI 2 "nonmemory_operand" "n,a")) + (clobber (match_scratch:SI 3 "=X,&a"))] + "!TARGET_64BIT" + "* +{ + switch (which_alternative) + { + case 0: + return \"mvc\\t%O0(%b2+1,%R0),%1\"; + + case 1: + output_asm_insn (\"bras\\t%3,.+10\", operands); + output_asm_insn (\"mvc\\t%O0(1,%R0),%1\", operands); + return \"ex\\t%2,0(%3)\"; + + default: + abort (); + } +}" + [(set_attr "op_type" "SS,NN") + (set_attr "atype" "mem,mem") + (set_attr "length" "*,14")]) -; Move a block that is more than 256 bytes in lenght or length in register +; Move a block that is a multiple of 256 bytes in length -(define_insn "movstrdix_64" - [(use (match_operand:DI 4 "register_operand" "a")) +(define_insn "movstrdi_long" + [(set (match_operand:DI 4 "register_operand" "=d") + (const_int 0)) (set (match_operand:DI 0 "register_operand" "=a") (plus:DI (match_operand:DI 2 "register_operand" "0") - (and:DI (match_dup 4) (const_int -256)))) + (ashift:DI (match_operand:DI 5 "register_operand" "4") + (const_int 8)))) (set (match_operand:DI 1 "register_operand" "=a") (plus:DI (match_operand:DI 3 "register_operand" "1") - (and:DI (match_dup 4) (const_int -256)))) + (ashift:DI (match_dup 5) (const_int 8)))) (set (mem:BLK (match_dup 2)) (mem:BLK (match_dup 3))) - (clobber (match_scratch:DI 5 "=&a")) - (clobber (reg:CC 33))] - "" + (use (match_dup 5))] + "TARGET_64BIT" "* { - rtx xop[4]; - xop[0] = gen_label_rtx (); - xop[1] = gen_label_rtx (); - xop[2] = gen_label_rtx (); - xop[3] = operands[5]; - output_asm_insn (\"srag\\t%5,%4,8\", operands); - output_asm_insn (\"jz\\t%l1\", xop); - ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\", - CODE_LABEL_NUMBER (xop[0])); output_asm_insn (\"mvc\\t0(256,%0),0(%1)\", operands); output_asm_insn (\"la\\t%0,256(%0)\", operands); output_asm_insn (\"la\\t%1,256(%1)\", operands); - output_asm_insn (\"brct\\t%3,%l0\", xop); - ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\", - CODE_LABEL_NUMBER (xop[1])); - output_asm_insn (\"bras\\t%3,%l2\", xop); - output_asm_insn (\"mvc\\t0(1,%0),0(%1)\", operands); - ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\", - CODE_LABEL_NUMBER (xop[2])); - return \"ex\\t%4,0(%5)\"; + return \"brct\\t%4,.-14\"; }" [(set_attr "op_type" "NN") (set_attr "atype" "mem") - (set_attr "length" "44")]) + (set_attr "length" "18")]) -(define_insn "movstrsix_31" - [(use (match_operand:SI 4 "register_operand" "a")) +(define_insn "movstrsi_long" + [(set (match_operand:SI 4 "register_operand" "=d") + (const_int 0)) (set (match_operand:SI 0 "register_operand" "=a") (plus:SI (match_operand:SI 2 "register_operand" "0") - (and:SI (match_dup 4) (const_int -256)))) + (ashift:SI (match_operand:SI 5 "register_operand" "4") + (const_int 8)))) (set (match_operand:SI 1 "register_operand" "=a") (plus:SI (match_operand:SI 3 "register_operand" "1") - (and:SI (match_dup 4) (const_int -256)))) + (ashift:SI (match_dup 5) (const_int 8)))) (set (mem:BLK (match_dup 2)) (mem:BLK (match_dup 3))) - (clobber (match_scratch:SI 5 "=&a")) - (clobber (reg:CC 33))] - "" + (use (match_dup 5))] + "!TARGET_64BIT" "* { - rtx xop[4]; - xop[0] = gen_label_rtx (); - xop[1] = gen_label_rtx (); - xop[2] = gen_label_rtx (); - xop[3] = operands[5]; - output_asm_insn (\"lr\\t%5,%4\", operands); - output_asm_insn (\"sra\\t%5,8\", operands); - output_asm_insn (\"jz\\t%l1\", xop); - ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\", - CODE_LABEL_NUMBER (xop[0])); output_asm_insn (\"mvc\\t0(256,%0),0(%1)\", operands); output_asm_insn (\"la\\t%0,256(%0)\", operands); output_asm_insn (\"la\\t%1,256(%1)\", operands); - output_asm_insn (\"brct\\t%3,%l0\", xop); - ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\", - CODE_LABEL_NUMBER (xop[1])); - output_asm_insn (\"bras\\t%3,%l2\", xop); - output_asm_insn (\"mvc\\t0(1,%0),0(%1)\", operands); - ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\", - CODE_LABEL_NUMBER (xop[2])); - return \"ex\\t%4,0(%5)\"; + return \"brct\\t%4,.-14\"; }" - [(set_attr "op_type" "NN") - (set_attr "length" "42") - (set_attr "atype" "mem")]) + [(set_attr "op_type" "NN") + (set_attr "atype" "mem") + (set_attr "length" "18")]) ; Move a block that is larger than 255 bytes in length. @@ -3836,6 +3864,7 @@ operands[4] = gen_reg_rtx(TImode); emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4])); emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]); + emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx); insn = emit_insn (gen_divmodtidi3 (operands[4], operands[4], operands[2])); REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); @@ -5322,8 +5351,7 @@ (define_insn "rotldi3" [(set (match_operand:DI 0 "register_operand" "=d,d") (rotate:DI (match_operand:DI 1 "register_operand" "d,d") - (match_operand:DI 2 "nonmemory_operand" "J,a"))) - (clobber (reg:CC 33))] + (match_operand:SI 2 "nonmemory_operand" "J,a")))] "TARGET_64BIT" "@ rllg\\t%0,%1,%c2 @@ -5337,8 +5365,7 @@ (define_insn "rotlsi3" [(set (match_operand:SI 0 "register_operand" "=d,d") (rotate:SI (match_operand:SI 1 "register_operand" "d,d") - (match_operand:SI 2 "nonmemory_operand" "J,a"))) - (clobber (reg:CC 33))] + (match_operand:SI 2 "nonmemory_operand" "J,a")))] "TARGET_64BIT" "@ rll\\t%0,%1,%c2 @@ -5349,26 +5376,22 @@ ;; ;;- Arithmetic shift instructions. ;; -;; for left shifts always setal shifts are used (ANSI-C) ; ; ashldi3 instruction pattern(s). ; (define_expand "ashldi3" - [(parallel - [(set (match_operand:DI 0 "register_operand" "") - (ashift:DI (match_operand:DI 1 "register_operand" "") - (match_operand:SI 2 "nonmemory_operand" ""))) - (clobber (reg:CC 33))])] + [(set (match_operand:DI 0 "register_operand" "") + (ashift:DI (match_operand:DI 1 "register_operand" "") + (match_operand:SI 2 "nonmemory_operand" "")))] "" "") (define_insn "*ashldi3_31" [(set (match_operand:DI 0 "register_operand" "=d,d") (ashift:DI (match_operand:DI 1 "register_operand" "0,0") - (match_operand:SI 2 "nonmemory_operand" "J,a"))) - (clobber (reg:CC 33))] + (match_operand:SI 2 "nonmemory_operand" "J,a")))] "!TARGET_64BIT" "@ sldl\\t%0,%c2 @@ -5376,10 +5399,9 @@ [(set_attr "op_type" "RS")]) (define_insn "*ashldi3_64" - [(set (match_operand:DI 0 "register_operand" "=d,d") + [(set (match_operand:DI 0 "register_operand" "=d,d") (ashift:DI (match_operand:DI 1 "register_operand" "d,d") - (match_operand:SI 2 "nonmemory_operand" "J,a"))) - (clobber (reg:CC 33))] + (match_operand:SI 2 "nonmemory_operand" "J,a")))] "TARGET_64BIT" "@ sllg\\t%0,%1,%2 @@ -5399,6 +5421,31 @@ "" "") +(define_insn "*ashrdi3_cc_31" + [(set (reg 33) + (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0") + (match_operand:SI 2 "nonmemory_operand" "J,a")) + (const_int 0))) + (set (match_operand:DI 0 "register_operand" "=d,d") + (ashiftrt:DI (match_dup 1) (match_dup 2)))] + "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)" + "@ + srda\\t%0,%c2 + srda\\t%0,0(%2)" + [(set_attr "op_type" "RS")]) + +(define_insn "*ashrdi3_cconly_31" + [(set (reg 33) + (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0") + (match_operand:SI 2 "nonmemory_operand" "J,a")) + (const_int 0))) + (clobber (match_scratch:DI 0 "=d,d"))] + "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)" + "@ + srda\\t%0,%c2 + srda\\t%0,0(%2)" + [(set_attr "op_type" "RS")]) + (define_insn "*ashrdi3_31" [(set (match_operand:DI 0 "register_operand" "=d,d") (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0") @@ -5410,6 +5457,31 @@ srda\\t%0,0(%2)" [(set_attr "op_type" "RS")]) +(define_insn "*ashrdi3_cc_64" + [(set (reg 33) + (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d") + (match_operand:SI 2 "nonmemory_operand" "J,a")) + (const_int 0))) + (set (match_operand:DI 0 "register_operand" "=d,d") + (ashiftrt:DI (match_dup 1) (match_dup 2)))] + "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" + "@ + srag\\t%0,%1,%c2 + srag\\t%0,%1,0(%2)" + [(set_attr "op_type" "RSE")]) + +(define_insn "*ashrdi3_cconly_64" + [(set (reg 33) + (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d") + (match_operand:SI 2 "nonmemory_operand" "J,a")) + (const_int 0))) + (clobber (match_scratch:DI 0 "=d,d"))] + "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" + "@ + srag\\t%0,%1,%c2 + srag\\t%0,%1,0(%2)" + [(set_attr "op_type" "RSE")]) + (define_insn "*ashrdi3_64" [(set (match_operand:DI 0 "register_operand" "=d,d") (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d") @@ -5424,13 +5496,11 @@ ; ; ashlsi3 instruction pattern(s). ; -; all 32 bits has to be shifted (testcase co750c) (define_insn "ashlsi3" [(set (match_operand:SI 0 "register_operand" "=d,d") (ashift:SI (match_operand:SI 1 "register_operand" "0,0") - (match_operand:SI 2 "nonmemory_operand" "J,a"))) - (clobber (reg:CC 33))] + (match_operand:SI 2 "nonmemory_operand" "J,a")))] "" "@ sll\\t%0,%c2 @@ -5441,6 +5511,31 @@ ; ashrsi3 instruction pattern(s). ; +(define_insn "*ashrsi3_cc" + [(set (reg 33) + (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0") + (match_operand:SI 2 "nonmemory_operand" "J,a")) + (const_int 0))) + (set (match_operand:SI 0 "register_operand" "=d,d") + (ashiftrt:SI (match_dup 1) (match_dup 2)))] + "s390_match_ccmode(insn, CCSmode)" + "@ + sra\\t%0,%c2 + sra\\t%0,0(%2)" + [(set_attr "op_type" "RS")]) + +(define_insn "*ashrsi3_cconly" + [(set (reg 33) + (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0") + (match_operand:SI 2 "nonmemory_operand" "J,a")) + (const_int 0))) + (clobber (match_scratch:SI 0 "=d,d"))] + "s390_match_ccmode(insn, CCSmode)" + "@ + sra\\t%0,%c2 + sra\\t%0,0(%2)" + [(set_attr "op_type" "RS")]) + (define_insn "ashrsi3" [(set (match_operand:SI 0 "register_operand" "=d,d") (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0") @@ -5462,19 +5557,16 @@ ; (define_expand "lshrdi3" - [(parallel - [(set (match_operand:DI 0 "register_operand" "") - (lshiftrt:DI (match_operand:DI 1 "register_operand" "") - (match_operand:SI 2 "nonmemory_operand" ""))) - (clobber (reg:CC 33))])] + [(set (match_operand:DI 0 "register_operand" "") + (lshiftrt:DI (match_operand:DI 1 "register_operand" "") + (match_operand:SI 2 "nonmemory_operand" "")))] "" "") (define_insn "*lshrdi3_31" [(set (match_operand:DI 0 "register_operand" "=d,d") (lshiftrt:DI (match_operand:DI 1 "register_operand" "0,0") - (match_operand:SI 2 "nonmemory_operand" "J,a"))) - (clobber (reg:CC 33))] + (match_operand:SI 2 "nonmemory_operand" "J,a")))] "!TARGET_64BIT" "@ srdl\\t%0,%c2 @@ -5484,8 +5576,7 @@ (define_insn "*lshrdi3_64" [(set (match_operand:DI 0 "register_operand" "=d,d") (lshiftrt:DI (match_operand:DI 1 "register_operand" "d,d") - (match_operand:SI 2 "nonmemory_operand" "J,a"))) - (clobber (reg:CC 33))] + (match_operand:SI 2 "nonmemory_operand" "J,a")))] "TARGET_64BIT" "@ srlg\\t%0,%1,%c2 @@ -5499,8 +5590,7 @@ (define_insn "lshrsi3" [(set (match_operand:SI 0 "register_operand" "=d,d") (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0") - (match_operand:SI 2 "nonmemory_operand" "J,a"))) - (clobber (reg:CC 33))] + (match_operand:SI 2 "nonmemory_operand" "J,a")))] "" "@ srl\\t%0,%c2