From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Wed, 14 Oct 2015 03:09:53 +0000 (+0800)
Subject: integration/builder: fix building for SoCSDRAM-based targets when SDRAM is disabled
X-Git-Tag: 24jan2021_ls180~2106^2~22
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ecc4c573eb4cdeae64771565ca86ca8949579be6;p=litex.git

integration/builder: fix building for SoCSDRAM-based targets when SDRAM is disabled

Reported by Florent Kermarrec
---

diff --git a/misoc/integration/builder.py b/misoc/integration/builder.py
index 44138ea3..ef89eaf6 100644
--- a/misoc/integration/builder.py
+++ b/misoc/integration/builder.py
@@ -53,7 +53,7 @@ class Builder:
         flash_boot_address = getattr(self.soc, "flash_boot_address", None)
         csr_regions = self.soc.get_csr_regions()
         constants = self.soc.get_constants()
-        if isinstance(self.soc, soc_sdram.SoCSDRAM):
+        if isinstance(self.soc, soc_sdram.SoCSDRAM) and self.soc._sdram_phy:
             sdram_phy_settings = self.soc._sdram_phy[0].settings
         else:
             sdram_phy_settings = None