From: lkcl <lkcl@web>
Date: Mon, 2 Aug 2021 09:43:49 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~536
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ecc74230c8880bf3a4e55f3a86e91faa93c0869e;p=libreriscv.git

---

diff --git a/openpower/sv/branches.mdwn b/openpower/sv/branches.mdwn
index baff71632..6a5655d19 100644
--- a/openpower/sv/branches.mdwn
+++ b/openpower/sv/branches.mdwn
@@ -126,7 +126,7 @@ Pseudocode for Horizontal-First Mode:
                continue
            else
                testbit = SVRMmode.SNZ
-           # actual element test herr
+           # actual element test here
            el_cond_ok <- ¬(testbit ^ BO[1])
            # merge in the test
            if SVRMmode.ALL: