From: Dmitry Selyutin Date: Mon, 21 Nov 2022 17:36:57 +0000 (+0300) Subject: power_insn: support lru specifier X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=eccb22ec0a744643dc49e3a3316196a05ffe9430;p=openpower-isa.git power_insn: support lru specifier --- diff --git a/src/openpower/decoder/power_insn.py b/src/openpower/decoder/power_insn.py index ea8dc5c4..5fec824f 100644 --- a/src/openpower/decoder/power_insn.py +++ b/src/openpower/decoder/power_insn.py @@ -2974,6 +2974,17 @@ class SpecifierSLu(SpecifierBranch): rm.SLu = 1 +@_dataclasses.dataclass(eq=True, frozen=True) +class SpecifierLRu(SpecifierBranch): + @classmethod + def match(cls, desc, record): + return super().match(desc=desc, record=record, etalon="lru") + + def assemble(self, insn): + rm = insn.prefix.rm.select(record=self.record) + rm.LRu = 1 + + class Specifiers(tuple): SPECS = ( SpecifierW, @@ -2998,6 +3009,7 @@ class Specifiers(tuple): SpecifierSNZ, SpecifierSL, SpecifierSLu, + SpecifierLRu, ) def __new__(cls, items, record):