From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 16 Apr 2019 21:53:01 +0000 (-0700)
Subject: Fix wire numbering
X-Git-Tag: working-ls180~1208^2~331
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ece5c3ab38023abc251828b9379ea4eca9573abc;p=yosys.git

Fix wire numbering
---

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index 7c7697874..66ab3878e 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -589,11 +589,12 @@ struct XAigerWriter
 					if (cell->input(c.first)) {
 						box_inputs += c.second.size();
 						if (holes_cell) {
-							holes_wire = holes_module->wire(stringf("\\i%d", num_inputs++));
+							holes_wire = holes_module->wire(stringf("\\i%d", num_inputs));
 							if (!holes_wire) {
 								holes_wire = holes_module->addWire(stringf("\\i%d", num_inputs));
 								holes_wire->port_input = true;
 							}
+							++num_inputs;
 							holes_cell->setPort(c.first, holes_wire);
 						}
 					}