From: Curtis Dunham <Curtis.Dunham@arm.com>
Date: Wed, 23 Apr 2014 09:18:30 +0000 (-0400)
Subject: arm: Correctly display disassembly of vldmia/vstmia
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ecf774bc561f139a13539d40dde075710f89183c;p=gem5.git

arm: Correctly display disassembly of vldmia/vstmia

The MicroMemOp class generates the disassembly for both integer
and floating point instructions, but it would always print its
first operand as an integer register without considering that the
op may be a floating instruction in which case a float register
should be displayed instead.
---

diff --git a/src/arch/arm/insts/macromem.cc b/src/arch/arm/insts/macromem.cc
index 42cb98a7c..cd77d6d5f 100644
--- a/src/arch/arm/insts/macromem.cc
+++ b/src/arch/arm/insts/macromem.cc
@@ -1483,7 +1483,10 @@ MicroMemOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);
-    printReg(ss, ura);
+    if (isFloating())
+        printReg(ss, ura + FP_Reg_Base);
+    else
+        printReg(ss, ura);
     ss << ", [";
     printReg(ss, urb);
     ss << ", ";