From: Andreas Hansson Date: Mon, 23 Mar 2015 10:57:31 +0000 (-0400) Subject: tests: Final reclassification of quick regressions X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ed08dc31babd83c5c4a439b4d189599dfeea33d1;p=gem5.git tests: Final reclassification of quick regressions A few regressions were still considered long, but finished well within the 180 seconds. They are only a handful (mostly mcf in atomic). --HG-- rename : tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini rename : tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simerr => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simerr rename : tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simout => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simout rename : tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt rename : tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/system.terminal => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/system.terminal rename : tests/long/se/10.mcf/ref/arm/linux/simple-atomic/chair.cook.ppm => tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/chair.cook.ppm rename : tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini => tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/config.ini rename : tests/long/se/10.mcf/ref/arm/linux/simple-atomic/mcf.out => tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/mcf.out rename : tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simerr => tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/simerr rename : tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout => tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/simout rename : tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt => tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt rename : tests/long/se/10.mcf/ref/arm/linux/simple-timing/chair.cook.ppm => tests/quick/se/10.mcf/ref/arm/linux/simple-timing/chair.cook.ppm rename : tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini => tests/quick/se/10.mcf/ref/arm/linux/simple-timing/config.ini rename : tests/long/se/10.mcf/ref/arm/linux/simple-timing/mcf.out => tests/quick/se/10.mcf/ref/arm/linux/simple-timing/mcf.out rename : tests/long/se/10.mcf/ref/arm/linux/simple-timing/simerr => tests/quick/se/10.mcf/ref/arm/linux/simple-timing/simerr rename : tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout => tests/quick/se/10.mcf/ref/arm/linux/simple-timing/simout rename : tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt => tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt rename : tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini => tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini rename : tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/mcf.out => tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/mcf.out rename : tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simerr => tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/simerr rename : tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout => tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/simout rename : tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt => tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt rename : tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini => tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/config.ini rename : tests/long/se/10.mcf/ref/x86/linux/simple-atomic/mcf.out => tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/mcf.out rename : tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simerr => tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/simerr rename : tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout => tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/simout rename : tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt => tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt rename : tests/long/se/10.mcf/test.py => tests/quick/se/10.mcf/test.py rename : tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini => tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini rename : tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simerr => tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/simerr rename : tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simout => tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/simout rename : tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt => tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt rename : tests/long/se/30.eon/test.py => tests/quick/se/30.eon/test.py --- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini deleted file mode 100644 index 8c1381ed5..000000000 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini +++ /dev/null @@ -1,1361 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=true -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=LinuxArmSystem -children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain -atags_addr=134217728 -boot_loader=/dist/binaries/boot_emm.arm -boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 -boot_release_addr=65528 -cache_line_size=64 -clk_domain=system.clk_domain -dtb_filename=/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb -early_kernel_symbols=false -enable_context_switch_stats_dump=false -eventq_index=0 -flags_addr=469827632 -gic_cpu_addr=738205696 -have_generic_timer=false -have_large_asid_64=false -have_lpae=false -have_security=false -have_virtualization=false -highest_el_is_64=false -init_param=0 -kernel=/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 -kernel_addr_check=true -load_addr_mask=268435455 -load_offset=2147483648 -machine_type=VExpress_EMM -mem_mode=timing -mem_ranges=2147483648:2415919103 -memories=system.realview.nvmem system.physmem system.realview.vram -multi_proc=true -num_work_ids=16 -panic_on_oops=true -panic_on_panic=true -phys_addr_range_64=40 -readfile=/work/gem5.ext/tests/halt.sh -reset_addr_64=0 -symbolfile= -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[1] - -[system.bridge] -type=Bridge -clk_domain=system.clk_domain -delay=50000 -eventq_index=0 -ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 -req_size=16 -resp_size=16 -master=system.iobus.slave[0] -slave=system.membus.master[0] - -[system.cf0] -type=IdeDisk -children=image -delay=1000000 -driveID=master -eventq_index=0 -image=system.cf0.image - -[system.cf0.image] -type=CowDiskImage -children=child -child=system.cf0.image.child -eventq_index=0 -image_file= -read_only=false -table_size=65536 - -[system.cf0.image.child] -type=RawDiskImage -eventq_index=0 -image_file=/dist/disks/linux-aarch32-ael.img -read_only=true - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu0] -type=TimingSimpleCPU -children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer -branchPred=Null -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dstage2_mmu=system.cpu0.dstage2_mmu -dtb=system.cpu0.dtb -eventq_index=0 -function_trace=false -function_trace_start=0 -interrupts=system.cpu0.interrupts -isa=system.cpu0.isa -istage2_mmu=system.cpu0.istage2_mmu -itb=system.cpu0.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -switched_out=false -system=system -tracer=system.cpu0.tracer -workload= -dcache_port=system.cpu0.dcache.cpu_side -icache_port=system.cpu0.icache.cpu_side - -[system.cpu0.dcache] -type=BaseCache -children=tags -addr_ranges=0:18446744073709551615 -assoc=4 -clk_domain=system.cpu_clk_domain -eventq_index=0 -forward_snoops=true -hit_latency=2 -is_top_level=true -max_miss_count=0 -mshrs=4 -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=32768 -system=system -tags=system.cpu0.dcache.tags -tgts_per_mshr=20 -two_queue=false -write_buffers=8 -cpu_side=system.cpu0.dcache_port -mem_side=system.toL2Bus.slave[1] - -[system.cpu0.dcache.tags] -type=LRU -assoc=4 -block_size=64 -clk_domain=system.cpu_clk_domain -eventq_index=0 -hit_latency=2 -sequential_access=false -size=32768 - -[system.cpu0.dstage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb -tlb=system.cpu0.dtb - -[system.cpu0.dstage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -walker=system.cpu0.dstage2_mmu.stage2_tlb.walker - -[system.cpu0.dstage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -sys=system -port=system.toL2Bus.slave[5] - -[system.cpu0.dtb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -walker=system.cpu0.dtb.walker - -[system.cpu0.dtb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -sys=system -port=system.toL2Bus.slave[3] - -[system.cpu0.icache] -type=BaseCache -children=tags -addr_ranges=0:18446744073709551615 -assoc=1 -clk_domain=system.cpu_clk_domain -eventq_index=0 -forward_snoops=true -hit_latency=2 -is_top_level=true -max_miss_count=0 -mshrs=4 -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=32768 -system=system -tags=system.cpu0.icache.tags -tgts_per_mshr=20 -two_queue=false -write_buffers=8 -cpu_side=system.cpu0.icache_port -mem_side=system.toL2Bus.slave[0] - -[system.cpu0.icache.tags] -type=LRU -assoc=1 -block_size=64 -clk_domain=system.cpu_clk_domain -eventq_index=0 -hit_latency=2 -sequential_access=false -size=32768 - -[system.cpu0.interrupts] -type=ArmInterrupts -eventq_index=0 - -[system.cpu0.isa] -type=ArmISA -eventq_index=0 -fpsid=1090793632 -id_aa64afr0_el1=0 -id_aa64afr1_el1=0 -id_aa64dfr0_el1=1052678 -id_aa64dfr1_el1=0 -id_aa64isar0_el1=0 -id_aa64isar1_el1=0 -id_aa64mmfr0_el1=15728642 -id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=17 -id_aa64pfr1_el1=0 -id_isar0=34607377 -id_isar1=34677009 -id_isar2=555950401 -id_isar3=17899825 -id_isar4=268501314 -id_isar5=0 -id_mmfr0=270536963 -id_mmfr1=0 -id_mmfr2=19070976 -id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 -midr=1091551472 -pmu=Null -system=system - -[system.cpu0.istage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb -tlb=system.cpu0.itb - -[system.cpu0.istage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -walker=system.cpu0.istage2_mmu.stage2_tlb.walker - -[system.cpu0.istage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -sys=system -port=system.toL2Bus.slave[4] - -[system.cpu0.itb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -walker=system.cpu0.itb.walker - -[system.cpu0.itb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -sys=system -port=system.toL2Bus.slave[2] - -[system.cpu0.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu1] -type=TimingSimpleCPU -children=dstage2_mmu dtb isa istage2_mmu itb tracer -branchPred=Null -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dstage2_mmu=system.cpu1.dstage2_mmu -dtb=system.cpu1.dtb -eventq_index=0 -function_trace=false -function_trace_start=0 -interrupts=Null -isa=system.cpu1.isa -istage2_mmu=system.cpu1.istage2_mmu -itb=system.cpu1.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -switched_out=true -system=system -tracer=system.cpu1.tracer -workload= - -[system.cpu1.dstage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb -tlb=system.cpu1.dtb - -[system.cpu1.dstage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -walker=system.cpu1.dstage2_mmu.stage2_tlb.walker - -[system.cpu1.dstage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -sys=system - -[system.cpu1.dtb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -walker=system.cpu1.dtb.walker - -[system.cpu1.dtb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -sys=system - -[system.cpu1.isa] -type=ArmISA -eventq_index=0 -fpsid=1090793632 -id_aa64afr0_el1=0 -id_aa64afr1_el1=0 -id_aa64dfr0_el1=1052678 -id_aa64dfr1_el1=0 -id_aa64isar0_el1=0 -id_aa64isar1_el1=0 -id_aa64mmfr0_el1=15728642 -id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=17 -id_aa64pfr1_el1=0 -id_isar0=34607377 -id_isar1=34677009 -id_isar2=555950401 -id_isar3=17899825 -id_isar4=268501314 -id_isar5=0 -id_mmfr0=270536963 -id_mmfr1=0 -id_mmfr2=19070976 -id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 -midr=1091551472 -pmu=Null -system=system - -[system.cpu1.istage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb -tlb=system.cpu1.itb - -[system.cpu1.istage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -walker=system.cpu1.istage2_mmu.stage2_tlb.walker - -[system.cpu1.istage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -sys=system - -[system.cpu1.itb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -walker=system.cpu1.itb.walker - -[system.cpu1.itb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -sys=system - -[system.cpu1.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.intrctrl] -type=IntrControl -eventq_index=0 -sys=system - -[system.iobus] -type=NoncoherentXBar -clk_domain=system.clk_domain -eventq_index=0 -header_cycles=1 -use_default_range=true -width=8 -default=system.realview.pciconfig.pio -master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side -slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma - -[system.iocache] -type=BaseCache -children=tags -addr_ranges=2147483648:2415919103 -assoc=8 -clk_domain=system.clk_domain -eventq_index=0 -forward_snoops=false -hit_latency=50 -is_top_level=true -max_miss_count=0 -mshrs=20 -prefetch_on_access=false -prefetcher=Null -response_latency=50 -sequential_access=false -size=1024 -system=system -tags=system.iocache.tags -tgts_per_mshr=12 -two_queue=false -write_buffers=8 -cpu_side=system.iobus.master[27] -mem_side=system.membus.slave[3] - -[system.iocache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.clk_domain -eventq_index=0 -hit_latency=50 -sequential_access=false -size=1024 - -[system.l2c] -type=BaseCache -children=tags -addr_ranges=0:18446744073709551615 -assoc=8 -clk_domain=system.cpu_clk_domain -eventq_index=0 -forward_snoops=true -hit_latency=20 -is_top_level=false -max_miss_count=0 -mshrs=20 -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=4194304 -system=system -tags=system.l2c.tags -tgts_per_mshr=12 -two_queue=false -write_buffers=8 -cpu_side=system.toL2Bus.master[0] -mem_side=system.membus.slave[2] - -[system.l2c.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -eventq_index=0 -hit_latency=20 -sequential_access=false -size=4194304 - -[system.membus] -type=CoherentXBar -children=badaddr_responder -clk_domain=system.clk_domain -eventq_index=0 -header_cycles=1 -snoop_filter=Null -system=system -use_default_range=false -width=8 -default=system.membus.badaddr_responder.pio -master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port -slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side - -[system.membus.badaddr_responder] -type=IsaFake -clk_domain=system.clk_domain -eventq_index=0 -fake_mem=false -pio_addr=0 -pio_latency=100000 -pio_size=8 -ret_bad_addr=true -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access=warn -pio=system.membus.default - -[system.physmem] -type=DRAMCtrl -IDD0=0.075000 -IDD02=0.000000 -IDD2N=0.050000 -IDD2N2=0.000000 -IDD2P0=0.000000 -IDD2P02=0.000000 -IDD2P1=0.000000 -IDD2P12=0.000000 -IDD3N=0.057000 -IDD3N2=0.000000 -IDD3P0=0.000000 -IDD3P02=0.000000 -IDD3P1=0.000000 -IDD3P12=0.000000 -IDD4R=0.187000 -IDD4R2=0.000000 -IDD4W=0.165000 -IDD4W2=0.000000 -IDD5=0.220000 -IDD52=0.000000 -IDD6=0.000000 -IDD62=0.000000 -VDD=1.500000 -VDD2=0.000000 -activation_limit=4 -addr_mapping=RoRaBaChCo -bank_groups_per_rank=0 -banks_per_rank=8 -burst_length=8 -channels=1 -clk_domain=system.clk_domain -conf_table_reported=true -device_bus_width=8 -device_rowbuffer_size=1024 -device_size=536870912 -devices_per_rank=8 -dll=true -eventq_index=0 -in_addr_map=true -max_accesses_per_row=16 -mem_sched_policy=frfcfs -min_writes_per_switch=16 -null=false -page_policy=open_adaptive -range=2147483648:2415919103 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10000 -static_frontend_latency=10000 -tBURST=5000 -tCCD_L=0 -tCK=1250 -tCL=13750 -tCS=2500 -tRAS=35000 -tRCD=13750 -tREFI=7800000 -tRFC=260000 -tRP=13750 -tRRD=6000 -tRRD_L=0 -tRTP=7500 -tRTW=2500 -tWR=15000 -tWTR=7500 -tXAW=30000 -tXP=0 -tXPDLL=0 -tXS=0 -tXSDLL=0 -write_buffer_size=64 -write_high_thresh_perc=85 -write_low_thresh_perc=50 -port=system.membus.master[5] - -[system.realview] -type=RealView -children=aaci_fake cf_ctrl clcd energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake -eventq_index=0 -intrctrl=system.intrctrl -pci_cfg_base=805306368 -pci_cfg_gen_offsets=false -pci_io_base=0 -system=system - -[system.realview.aaci_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -eventq_index=0 -ignore_access=false -pio_addr=470024192 -pio_latency=100000 -system=system -pio=system.iobus.master[18] - -[system.realview.cf_ctrl] -type=IdeController -BAR0=471465984 -BAR0LegacyIO=true -BAR0Size=256 -BAR1=471466240 -BAR1LegacyIO=true -BAR1Size=4096 -BAR2=1 -BAR2LegacyIO=false -BAR2Size=8 -BAR3=1 -BAR3LegacyIO=false -BAR3Size=4 -BAR4=1 -BAR4LegacyIO=false -BAR4Size=16 -BAR5=1 -BAR5LegacyIO=false -BAR5Size=0 -BIST=0 -CacheLineSize=0 -CapabilityPtr=0 -CardbusCIS=0 -ClassCode=1 -Command=1 -DeviceID=28945 -ExpansionROM=0 -HeaderType=0 -InterruptLine=31 -InterruptPin=1 -LatencyTimer=0 -LegacyIOBase=0 -MSICAPBaseOffset=0 -MSICAPCapId=0 -MSICAPMaskBits=0 -MSICAPMsgAddr=0 -MSICAPMsgCtrl=0 -MSICAPMsgData=0 -MSICAPMsgUpperAddr=0 -MSICAPNextCapability=0 -MSICAPPendingBits=0 -MSIXCAPBaseOffset=0 -MSIXCAPCapId=0 -MSIXCAPNextCapability=0 -MSIXMsgCtrl=0 -MSIXPbaOffset=0 -MSIXTableOffset=0 -MaximumLatency=0 -MinimumGrant=0 -PMCAPBaseOffset=0 -PMCAPCapId=0 -PMCAPCapabilities=0 -PMCAPCtrlStatus=0 -PMCAPNextCapability=0 -PXCAPBaseOffset=0 -PXCAPCapId=0 -PXCAPCapabilities=0 -PXCAPDevCap2=0 -PXCAPDevCapabilities=0 -PXCAPDevCtrl=0 -PXCAPDevCtrl2=0 -PXCAPDevStatus=0 -PXCAPLinkCap=0 -PXCAPLinkCtrl=0 -PXCAPLinkStatus=0 -PXCAPNextCapability=0 -ProgIF=133 -Revision=0 -Status=640 -SubClassCode=1 -SubsystemID=0 -SubsystemVendorID=0 -VendorID=32902 -clk_domain=system.clk_domain -config_latency=20000 -ctrl_offset=2 -disks= -eventq_index=0 -io_shift=2 -pci_bus=2 -pci_dev=0 -pci_func=0 -pio_latency=30000 -platform=system.realview -system=system -config=system.iobus.master[9] -dma=system.iobus.slave[2] -pio=system.iobus.master[8] - -[system.realview.clcd] -type=Pl111 -amba_id=1315089 -clk_domain=system.clk_domain -enable_capture=true -eventq_index=0 -gic=system.realview.gic -int_num=46 -pio_addr=471793664 -pio_latency=10000 -pixel_clock=41667 -system=system -vnc=system.vncserver -dma=system.iobus.slave[1] -pio=system.iobus.master[4] - -[system.realview.energy_ctrl] -type=EnergyCtrl -clk_domain=system.clk_domain -dvfs_handler=system.dvfs_handler -eventq_index=0 -pio_addr=470286336 -pio_latency=100000 -system=system -pio=system.iobus.master[22] - -[system.realview.ethernet] -type=IGbE -BAR0=0 -BAR0LegacyIO=false -BAR0Size=131072 -BAR1=0 -BAR1LegacyIO=false -BAR1Size=0 -BAR2=0 -BAR2LegacyIO=false -BAR2Size=0 -BAR3=0 -BAR3LegacyIO=false -BAR3Size=0 -BAR4=0 -BAR4LegacyIO=false -BAR4Size=0 -BAR5=0 -BAR5LegacyIO=false -BAR5Size=0 -BIST=0 -CacheLineSize=0 -CapabilityPtr=0 -CardbusCIS=0 -ClassCode=2 -Command=0 -DeviceID=4213 -ExpansionROM=0 -HeaderType=0 -InterruptLine=1 -InterruptPin=1 -LatencyTimer=0 -LegacyIOBase=0 -MSICAPBaseOffset=0 -MSICAPCapId=0 -MSICAPMaskBits=0 -MSICAPMsgAddr=0 -MSICAPMsgCtrl=0 -MSICAPMsgData=0 -MSICAPMsgUpperAddr=0 -MSICAPNextCapability=0 -MSICAPPendingBits=0 -MSIXCAPBaseOffset=0 -MSIXCAPCapId=0 -MSIXCAPNextCapability=0 -MSIXMsgCtrl=0 -MSIXPbaOffset=0 -MSIXTableOffset=0 -MaximumLatency=0 -MinimumGrant=255 -PMCAPBaseOffset=0 -PMCAPCapId=0 -PMCAPCapabilities=0 -PMCAPCtrlStatus=0 -PMCAPNextCapability=0 -PXCAPBaseOffset=0 -PXCAPCapId=0 -PXCAPCapabilities=0 -PXCAPDevCap2=0 -PXCAPDevCapabilities=0 -PXCAPDevCtrl=0 -PXCAPDevCtrl2=0 -PXCAPDevStatus=0 -PXCAPLinkCap=0 -PXCAPLinkCtrl=0 -PXCAPLinkStatus=0 -PXCAPNextCapability=0 -ProgIF=0 -Revision=0 -Status=0 -SubClassCode=0 -SubsystemID=4104 -SubsystemVendorID=32902 -VendorID=32902 -clk_domain=system.clk_domain -config_latency=20000 -eventq_index=0 -fetch_comp_delay=10000 -fetch_delay=10000 -hardware_address=00:90:00:00:00:01 -pci_bus=0 -pci_dev=0 -pci_func=0 -phy_epid=896 -phy_pid=680 -pio_latency=30000 -platform=system.realview -rx_desc_cache_size=64 -rx_fifo_size=393216 -rx_write_delay=0 -system=system -tx_desc_cache_size=64 -tx_fifo_size=393216 -tx_read_delay=0 -wb_comp_delay=10000 -wb_delay=10000 -config=system.iobus.master[26] -dma=system.iobus.slave[4] -pio=system.iobus.master[25] - -[system.realview.generic_timer] -type=GenericTimer -eventq_index=0 -gic=system.realview.gic -int_num=29 -system=system - -[system.realview.gic] -type=Pl390 -clk_domain=system.clk_domain -cpu_addr=738205696 -cpu_pio_delay=10000 -dist_addr=738201600 -dist_pio_delay=10000 -eventq_index=0 -int_latency=10000 -it_lines=128 -msix_addr=0 -platform=system.realview -system=system -pio=system.membus.master[2] - -[system.realview.hdlcd] -type=HDLcd -amba_id=1314816 -clk_domain=system.clk_domain -enable_capture=true -eventq_index=0 -gic=system.realview.gic -int_num=117 -pio_addr=721420288 -pio_latency=10000 -pixel_clock=7299 -system=system -vnc=system.vncserver -dma=system.membus.slave[0] -pio=system.iobus.master[5] - -[system.realview.ide] -type=IdeController -BAR0=1 -BAR0LegacyIO=false -BAR0Size=8 -BAR1=1 -BAR1LegacyIO=false -BAR1Size=4 -BAR2=1 -BAR2LegacyIO=false -BAR2Size=8 -BAR3=1 -BAR3LegacyIO=false -BAR3Size=4 -BAR4=1 -BAR4LegacyIO=false -BAR4Size=16 -BAR5=1 -BAR5LegacyIO=false -BAR5Size=0 -BIST=0 -CacheLineSize=0 -CapabilityPtr=0 -CardbusCIS=0 -ClassCode=1 -Command=0 -DeviceID=28945 -ExpansionROM=0 -HeaderType=0 -InterruptLine=2 -InterruptPin=2 -LatencyTimer=0 -LegacyIOBase=0 -MSICAPBaseOffset=0 -MSICAPCapId=0 -MSICAPMaskBits=0 -MSICAPMsgAddr=0 -MSICAPMsgCtrl=0 -MSICAPMsgData=0 -MSICAPMsgUpperAddr=0 -MSICAPNextCapability=0 -MSICAPPendingBits=0 -MSIXCAPBaseOffset=0 -MSIXCAPCapId=0 -MSIXCAPNextCapability=0 -MSIXMsgCtrl=0 -MSIXPbaOffset=0 -MSIXTableOffset=0 -MaximumLatency=0 -MinimumGrant=0 -PMCAPBaseOffset=0 -PMCAPCapId=0 -PMCAPCapabilities=0 -PMCAPCtrlStatus=0 -PMCAPNextCapability=0 -PXCAPBaseOffset=0 -PXCAPCapId=0 -PXCAPCapabilities=0 -PXCAPDevCap2=0 -PXCAPDevCapabilities=0 -PXCAPDevCtrl=0 -PXCAPDevCtrl2=0 -PXCAPDevStatus=0 -PXCAPLinkCap=0 -PXCAPLinkCtrl=0 -PXCAPLinkStatus=0 -PXCAPNextCapability=0 -ProgIF=133 -Revision=0 -Status=640 -SubClassCode=1 -SubsystemID=0 -SubsystemVendorID=0 -VendorID=32902 -clk_domain=system.clk_domain -config_latency=20000 -ctrl_offset=0 -disks=system.cf0 -eventq_index=0 -io_shift=0 -pci_bus=0 -pci_dev=1 -pci_func=0 -pio_latency=30000 -platform=system.realview -system=system -config=system.iobus.master[24] -dma=system.iobus.slave[3] -pio=system.iobus.master[23] - -[system.realview.kmi0] -type=Pl050 -amba_id=1314896 -clk_domain=system.clk_domain -eventq_index=0 -gic=system.realview.gic -int_delay=1000000 -int_num=44 -is_mouse=false -pio_addr=470155264 -pio_latency=100000 -system=system -vnc=system.vncserver -pio=system.iobus.master[6] - -[system.realview.kmi1] -type=Pl050 -amba_id=1314896 -clk_domain=system.clk_domain -eventq_index=0 -gic=system.realview.gic -int_delay=1000000 -int_num=45 -is_mouse=true -pio_addr=470220800 -pio_latency=100000 -system=system -vnc=system.vncserver -pio=system.iobus.master[7] - -[system.realview.l2x0_fake] -type=IsaFake -clk_domain=system.clk_domain -eventq_index=0 -fake_mem=false -pio_addr=739246080 -pio_latency=100000 -pio_size=4095 -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[12] - -[system.realview.lan_fake] -type=IsaFake -clk_domain=system.clk_domain -eventq_index=0 -fake_mem=false -pio_addr=436207616 -pio_latency=100000 -pio_size=65535 -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[19] - -[system.realview.local_cpu_timer] -type=CpuLocalTimer -clk_domain=system.clk_domain -eventq_index=0 -gic=system.realview.gic -int_num_timer=29 -int_num_watchdog=30 -pio_addr=738721792 -pio_latency=100000 -system=system -pio=system.membus.master[3] - -[system.realview.mmc_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -eventq_index=0 -ignore_access=false -pio_addr=470089728 -pio_latency=100000 -system=system -pio=system.iobus.master[21] - -[system.realview.nvmem] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=false -eventq_index=0 -in_addr_map=true -latency=30000 -latency_var=0 -null=false -range=0:67108863 -port=system.membus.master[1] - -[system.realview.pciconfig] -type=PciConfigAll -bus=0 -clk_domain=system.clk_domain -eventq_index=0 -pio_addr=0 -pio_latency=30000 -platform=system.realview -size=268435456 -system=system -pio=system.iobus.default - -[system.realview.realview_io] -type=RealViewCtrl -clk_domain=system.clk_domain -eventq_index=0 -idreg=35979264 -pio_addr=469827584 -pio_latency=100000 -proc_id0=335544320 -proc_id1=335544320 -system=system -pio=system.iobus.master[1] - -[system.realview.rtc] -type=PL031 -amba_id=3412017 -clk_domain=system.clk_domain -eventq_index=0 -gic=system.realview.gic -int_delay=100000 -int_num=36 -pio_addr=471269376 -pio_latency=100000 -system=system -time=Thu Jan 1 00:00:00 2009 -pio=system.iobus.master[10] - -[system.realview.sp810_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -eventq_index=0 -ignore_access=true -pio_addr=469893120 -pio_latency=100000 -system=system -pio=system.iobus.master[16] - -[system.realview.timer0] -type=Sp804 -amba_id=1316868 -clk_domain=system.clk_domain -clock0=1000000 -clock1=1000000 -eventq_index=0 -gic=system.realview.gic -int_num0=34 -int_num1=34 -pio_addr=470876160 -pio_latency=100000 -system=system -pio=system.iobus.master[2] - -[system.realview.timer1] -type=Sp804 -amba_id=1316868 -clk_domain=system.clk_domain -clock0=1000000 -clock1=1000000 -eventq_index=0 -gic=system.realview.gic -int_num0=35 -int_num1=35 -pio_addr=470941696 -pio_latency=100000 -system=system -pio=system.iobus.master[3] - -[system.realview.uart] -type=Pl011 -clk_domain=system.clk_domain -end_on_eot=false -eventq_index=0 -gic=system.realview.gic -int_delay=100000 -int_num=37 -pio_addr=470351872 -pio_latency=100000 -platform=system.realview -system=system -terminal=system.terminal -pio=system.iobus.master[0] - -[system.realview.uart1_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -eventq_index=0 -ignore_access=false -pio_addr=470417408 -pio_latency=100000 -system=system -pio=system.iobus.master[13] - -[system.realview.uart2_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -eventq_index=0 -ignore_access=false -pio_addr=470482944 -pio_latency=100000 -system=system -pio=system.iobus.master[14] - -[system.realview.uart3_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -eventq_index=0 -ignore_access=false -pio_addr=470548480 -pio_latency=100000 -system=system -pio=system.iobus.master[15] - -[system.realview.usb_fake] -type=IsaFake -clk_domain=system.clk_domain -eventq_index=0 -fake_mem=false -pio_addr=452984832 -pio_latency=100000 -pio_size=131071 -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[20] - -[system.realview.vgic] -type=VGic -clk_domain=system.clk_domain -eventq_index=0 -gic=system.realview.gic -hv_addr=738213888 -pio_delay=10000 -platform=system.realview -ppint=25 -system=system -vcpu_addr=738222080 -pio=system.membus.master[4] - -[system.realview.vram] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=false -eventq_index=0 -in_addr_map=true -latency=30000 -latency_var=0 -null=false -range=402653184:436207615 -port=system.iobus.master[11] - -[system.realview.watchdog_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -eventq_index=0 -ignore_access=false -pio_addr=470745088 -pio_latency=100000 -system=system -pio=system.iobus.master[17] - -[system.terminal] -type=Terminal -eventq_index=0 -intr_control=system.intrctrl -number=0 -output=true -port=3456 - -[system.toL2Bus] -type=CoherentXBar -clk_domain=system.cpu_clk_domain -eventq_index=0 -header_cycles=1 -snoop_filter=Null -system=system -use_default_range=false -width=8 -master=system.l2c.cpu_side -slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port - -[system.vncserver] -type=VncServer -eventq_index=0 -frame_capture=false -number=0 -port=5900 - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simerr deleted file mode 100755 index 067647ddd..000000000 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simerr +++ /dev/null @@ -1,69 +0,0 @@ -warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) -warn: Sockets disabled, not accepting vnc client connections -warn: Sockets disabled, not accepting terminal connections -warn: Sockets disabled, not accepting gdb connections -warn: Existing EnergyCtrl, but no enabled DVFSHandler found. -warn: Not doing anything for miscreg ACTLR -warn: Not doing anything for write of miscreg ACTLR -warn: The clidr register always reports 0 caches. -warn: clidr LoUIS field of 0b001 to match current ARM implementations. -warn: The csselr register isn't implemented. -warn: instruction 'mcr dccmvau' unimplemented -warn: instruction 'mcr icimvau' unimplemented -warn: instruction 'mcr bpiallis' unimplemented -warn: instruction 'mcr icialluis' unimplemented -warn: instruction 'mcr dccimvac' unimplemented -warn: Tried to read RealView I/O at offset 0x60 that doesn't exist -warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist -warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist -warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist -warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist -warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist -warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist -warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist -warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist -warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist -warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4] -warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4] -warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0] -warn: Returning zero for read from miscreg pmcr -warn: Ignoring write to miscreg pmcntenclr -warn: Ignoring write to miscreg pmintenclr -warn: Ignoring write to miscreg pmovsr -warn: Ignoring write to miscreg pmcr -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simout deleted file mode 100755 index 28734ef64..000000000 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simout +++ /dev/null @@ -1,10 +0,0 @@ -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Oct 31 2014 10:01:44 -gem5 started Oct 31 2014 11:48:18 -gem5 executing on u200540-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-timing -re /work/gem5.ext/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-timing -Global frequency set at 1000000000000 ticks per second - 0: system.cpu0.isa: ISA system set to: 0x4989680 0x4989680 - 0: system.cpu1.isa: ISA system set to: 0x4989680 0x4989680 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt deleted file mode 100644 index 7478799f2..000000000 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt +++ /dev/null @@ -1,1915 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 2.903641 # Number of seconds simulated -sim_ticks 2903640922500 # Number of ticks simulated -final_tick 2903640922500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 705602 # Simulator instruction rate (inst/s) -host_op_rate 850741 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 18218787173 # Simulator tick rate (ticks/s) -host_mem_usage 616688 # Number of bytes of host memory used -host_seconds 159.38 # Real time elapsed on the host -sim_insts 112456119 # Number of instructions simulated -sim_ops 135587804 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 582564 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 3808480 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 602944 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5025476 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10021000 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 582564 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 602944 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1185508 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7434688 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 17516 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 8 # Number of bytes written to this memory -system.physmem.bytes_written::total 7452212 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 17556 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 60026 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 9421 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 78524 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 165551 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 116167 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory -system.physmem.num_writes::total 120548 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 66 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 44 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 200632 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1311622 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 88 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 207651 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1730750 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 331 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3451184 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 200632 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 207651 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 408283 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2560471 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6032 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2566506 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2560471 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 66 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 44 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 200632 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1317655 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 88 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 207651 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1730753 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 331 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6017690 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 165551 # Number of read requests accepted -system.physmem.writeReqs 156772 # Number of write requests accepted -system.physmem.readBursts 165551 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 156772 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10588736 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6528 # Total number of bytes read from write queue -system.physmem.bytesWritten 8522624 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10021000 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 9770548 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 102 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 23601 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4489 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9899 # Per bank write bursts -system.physmem.perBankRdBursts::1 9526 # Per bank write bursts -system.physmem.perBankRdBursts::2 9759 # Per bank write bursts -system.physmem.perBankRdBursts::3 9793 # Per bank write bursts -system.physmem.perBankRdBursts::4 18999 # Per bank write bursts -system.physmem.perBankRdBursts::5 10033 # Per bank write bursts -system.physmem.perBankRdBursts::6 10462 # Per bank write bursts -system.physmem.perBankRdBursts::7 10803 # Per bank write bursts -system.physmem.perBankRdBursts::8 9925 # Per bank write bursts -system.physmem.perBankRdBursts::9 10243 # Per bank write bursts -system.physmem.perBankRdBursts::10 9858 # Per bank write bursts -system.physmem.perBankRdBursts::11 9250 # Per bank write bursts -system.physmem.perBankRdBursts::12 9247 # Per bank write bursts -system.physmem.perBankRdBursts::13 9475 # Per bank write bursts -system.physmem.perBankRdBursts::14 9028 # Per bank write bursts -system.physmem.perBankRdBursts::15 9149 # Per bank write bursts -system.physmem.perBankWrBursts::0 8258 # Per bank write bursts -system.physmem.perBankWrBursts::1 8244 # Per bank write bursts -system.physmem.perBankWrBursts::2 8572 # Per bank write bursts -system.physmem.perBankWrBursts::3 8149 # Per bank write bursts -system.physmem.perBankWrBursts::4 8563 # Per bank write bursts -system.physmem.perBankWrBursts::5 8536 # Per bank write bursts -system.physmem.perBankWrBursts::6 8718 # Per bank write bursts -system.physmem.perBankWrBursts::7 9117 # Per bank write bursts -system.physmem.perBankWrBursts::8 8657 # Per bank write bursts -system.physmem.perBankWrBursts::9 8771 # Per bank write bursts -system.physmem.perBankWrBursts::10 8610 # Per bank write bursts -system.physmem.perBankWrBursts::11 7990 # Per bank write bursts -system.physmem.perBankWrBursts::12 7949 # Per bank write bursts -system.physmem.perBankWrBursts::13 7964 # Per bank write bursts -system.physmem.perBankWrBursts::14 7531 # Per bank write bursts -system.physmem.perBankWrBursts::15 7537 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 32 # Number of times write queue was full causing retry -system.physmem.totGap 2903640597500 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 9558 # Read request sizes (log2) -system.physmem.readPktSize::3 14 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 155979 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 4381 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 152391 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 164623 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 542 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 272 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 178 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1636 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1852 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5271 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5453 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5489 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5477 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5778 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6926 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5746 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7269 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6043 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6071 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7760 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6386 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5989 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6226 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1272 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1286 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 2214 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 2179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1803 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1883 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 2499 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1872 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1797 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1557 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1902 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1747 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1424 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 1057 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 786 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 394 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 308 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 312 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 191 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 40 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 57876 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 330.211072 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 191.290947 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 346.940345 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 20714 35.79% 35.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14256 24.63% 60.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5208 9.00% 69.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3123 5.40% 74.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2440 4.22% 79.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1489 2.57% 81.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1071 1.85% 83.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1111 1.92% 85.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8464 14.62% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 57876 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5262 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 31.441087 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 579.786182 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 5260 99.96% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::40960-43007 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5262 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5262 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 25.307108 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.699141 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 47.946490 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-15 45 0.86% 0.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-31 4897 93.06% 93.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-47 79 1.50% 95.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-63 16 0.30% 95.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-79 14 0.27% 95.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-95 19 0.36% 96.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-111 31 0.59% 96.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-127 27 0.51% 97.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-143 13 0.25% 97.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-159 8 0.15% 97.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-175 3 0.06% 97.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-191 23 0.44% 98.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-207 14 0.27% 98.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-223 10 0.19% 98.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-239 3 0.06% 98.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-255 3 0.06% 98.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-271 3 0.06% 98.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-287 4 0.08% 99.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::288-303 8 0.15% 99.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::304-319 4 0.08% 99.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::320-335 3 0.06% 99.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::336-351 5 0.10% 99.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::352-367 8 0.15% 99.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::368-383 1 0.02% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::384-399 1 0.02% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::416-431 1 0.02% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::432-447 1 0.02% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::464-479 1 0.02% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::496-511 3 0.06% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::512-527 1 0.02% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::528-543 3 0.06% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::544-559 3 0.06% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::560-575 1 0.02% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::608-623 1 0.02% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::656-671 1 0.02% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::672-687 1 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::688-703 1 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::720-735 2 0.04% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5262 # Writes before turning the bus around for reads -system.physmem.totQLat 1437662314 # Total ticks spent queuing -system.physmem.totMemAccLat 4539831064 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 827245000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8689.46 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27439.46 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 3.65 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.94 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 3.45 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.36 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.05 # Data bus utilization in percentage -system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 10.50 # Average write queue length when enqueuing -system.physmem.readRowHits 136363 # Number of row buffer hits during reads -system.physmem.writeRowHits 104375 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.42 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.38 # Row buffer hit rate for writes -system.physmem.avgGap 9008480.93 # Average gap between requests -system.physmem.pageHitRate 80.62 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 229453560 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 125197875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 696337200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 441657360 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 189651686640 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 86953063950 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1665909868500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1944007265085 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.506799 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2771232360210 # Time in different power states -system.physmem_0.memoryStateTime::REF 96958940000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 35449523540 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 208089000 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 113540625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 594157200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 421258320 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 189651686640 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 84877892595 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1667730194250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1943596818630 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.365444 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2774279366726 # Time in different power states -system.physmem_1.memoryStateTime::REF 96958940000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 32402517024 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 7 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s) -system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). -system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). -system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. -system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. -system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 6899 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 6899 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 2220 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 4679 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 6899 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 6899 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 6899 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 5841 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 12315.228557 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 10506.489584 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 6688.963614 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-16383 4458 76.32% 76.32% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::16384-32767 1381 23.64% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::81920-98303 1 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 5841 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 937449500 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 937449500 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 937449500 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 3645 62.40% 62.40% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 2196 37.60% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 5841 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 6899 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 6899 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 5841 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 5841 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 12740 # Table walker requests started/completed, data/inst -system.cpu0.dtb.inst_hits 0 # ITB inst hits -system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 12462635 # DTB read hits -system.cpu0.dtb.read_misses 5988 # DTB read misses -system.cpu0.dtb.write_hits 9832923 # DTB write hits -system.cpu0.dtb.write_misses 911 # DTB write misses -system.cpu0.dtb.flush_tlb 2938 # Number of times complete TLB was flushed -system.cpu0.dtb.flush_tlb_mva 496 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 4660 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 940 # Number of TLB faults due to prefetch -system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 240 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 12468623 # DTB read accesses -system.cpu0.dtb.write_accesses 9833834 # DTB write accesses -system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 22295558 # DTB hits -system.cpu0.dtb.misses 6899 # DTB misses -system.cpu0.dtb.accesses 22302457 # DTB accesses -system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 3577 # Table walker walks requested -system.cpu0.itb.walker.walksShort 3577 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walksShortTerminationLevel::Level1 835 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 2742 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 3577 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 3577 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 3577 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 2726 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 12637.197359 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 10746.267304 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 6704.748097 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-8191 633 23.22% 23.22% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::8192-16383 1408 51.65% 74.87% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-24575 683 25.06% 99.93% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::81920-90111 1 0.04% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 2726 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 937122000 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 937122000 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 937122000 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 1891 69.37% 69.37% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 835 30.63% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 2726 # Table walker page sizes translated -system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3577 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3577 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2726 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2726 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 6303 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 58414032 # ITB inst hits -system.cpu0.itb.inst_misses 3577 # ITB inst misses -system.cpu0.itb.read_hits 0 # DTB read hits -system.cpu0.itb.read_misses 0 # DTB read misses -system.cpu0.itb.write_hits 0 # DTB write hits -system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 2938 # Number of times complete TLB was flushed -system.cpu0.itb.flush_tlb_mva 496 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2760 # Number of entries that have been flushed from TLB -system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu0.itb.read_accesses 0 # DTB read accesses -system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 58417609 # ITB inst accesses -system.cpu0.itb.hits 58414032 # DTB hits -system.cpu0.itb.misses 3577 # DTB misses -system.cpu0.itb.accesses 58417609 # DTB accesses -system.cpu0.numCycles 2904051621 # number of cpu cycles simulated -system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 56844590 # Number of instructions committed -system.cpu0.committedOps 68476862 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 60556147 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 5891 # Number of float alu accesses -system.cpu0.num_func_calls 5072041 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 7664286 # number of instructions that are conditional controls -system.cpu0.num_int_insts 60556147 # number of integer instructions -system.cpu0.num_fp_insts 5891 # number of float instructions -system.cpu0.num_int_register_reads 110162183 # number of times the integer registers were read -system.cpu0.num_int_register_writes 41899351 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 4609 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 1284 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 247668564 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 26017746 # number of times the CC registers were written -system.cpu0.num_mem_refs 22952183 # number of memory refs -system.cpu0.num_load_insts 12628752 # Number of load instructions -system.cpu0.num_store_insts 10323431 # Number of store instructions -system.cpu0.num_idle_cycles 2690582406.498001 # Number of idle cycles -system.cpu0.num_busy_cycles 213469214.501999 # Number of busy cycles -system.cpu0.not_idle_fraction 0.073507 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.926493 # Percentage of idle cycles -system.cpu0.Branches 13135796 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2207 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 47055843 67.15% 67.15% # Class of executed instruction -system.cpu0.op_class::IntMult 59396 0.08% 67.24% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 67.24% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 67.24% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 67.24% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 67.24% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 67.24% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 67.24% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 67.24% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 67.24% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 67.24% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 67.24% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 67.24% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 67.24% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 67.24% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 67.24% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 67.24% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 67.24% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 67.24% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 67.24% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 67.24% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.24% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.24% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.24% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.24% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 4431 0.01% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::MemRead 12628752 18.02% 85.27% # Class of executed instruction -system.cpu0.op_class::MemWrite 10323431 14.73% 100.00% # Class of executed instruction -system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 70074060 # Class of executed instruction -system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 3032 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 821716 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.827808 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 43234238 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 822228 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 52.581812 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 1008982250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 377.484524 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 134.343284 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.737274 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.262389 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.999664 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 373 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 82 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 177115546 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 177115546 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 11742107 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 11368313 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 23110420 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 9438605 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 9386535 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 18825140 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 200385 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 191808 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 392193 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 230728 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 212742 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 443470 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 239351 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 220930 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 460281 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 21180712 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 20754848 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 41935560 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 21381097 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 20946656 # number of overall hits -system.cpu0.dcache.overall_hits::total 42327753 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 202379 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 199779 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 402158 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 143306 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 155169 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 298475 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 60388 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 58192 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 118580 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 11633 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 10971 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 22604 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 345685 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 354948 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 700633 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 406073 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 413140 # number of overall misses -system.cpu0.dcache.overall_misses::total 819213 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 2998718242 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2978169130 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5976887372 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5523492960 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 6886936529 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 12410429489 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 144593750 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 135344000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 279937750 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 164000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 164000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 8522211202 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 9865105659 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 18387316861 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 8522211202 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 9865105659 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 18387316861 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 11944486 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 11568092 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 23512578 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 9581911 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 9541704 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 19123615 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 260773 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 250000 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 510773 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 242361 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 223713 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 466074 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 239353 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 220930 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 460283 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 21526397 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 21109796 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 42636193 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 21787170 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 21359796 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 43146966 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.016943 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.017270 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.017104 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.014956 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.016262 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.015608 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.231573 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.232768 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.232158 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.047999 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.049041 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.048499 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000008 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.016059 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.016814 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.016433 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.018638 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.019342 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.018987 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14817.338963 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14907.318237 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14862.037736 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38543.347522 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 44383.456290 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 41579.460554 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12429.618327 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12336.523562 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12384.434171 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 82000 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 82000 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 24653.112522 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 27793.101127 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 26243.863565 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 20986.894480 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 23878.360021 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 22445.098968 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 57 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 19 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 3 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.fast_writes 0 # number of fast writes performed -system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 687030 # number of writebacks -system.cpu0.dcache.writebacks::total 687030 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 287 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 373 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 660 # number of ReadReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 7066 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 7026 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14092 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 287 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu1.data 373 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 660 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 287 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu1.data 373 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 660 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 202092 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 199406 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 401498 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 143306 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 155169 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 298475 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 59468 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 57033 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 116501 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 4567 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 3945 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8512 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 345398 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 354575 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 699973 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 404866 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 411608 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 816474 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2687850000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2671783250 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5359633250 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5284681040 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 6621405971 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11906087011 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 749127008 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 719245636 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1468372644 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 55884250 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 49619250 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 105503500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 161000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 161000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7972531040 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 9293189221 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 17265720261 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8721658048 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 10012434857 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 18734092905 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2822172000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3011105500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5833277500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2259926000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2253271000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4513197000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5082098000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 5264376500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10346474500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016919 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.017238 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017076 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.014956 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.016262 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.015608 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.228045 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.228132 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.228088 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.018844 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.017634 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.018263 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000008 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016045 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.016797 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.016417 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018583 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.019270 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.018923 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13300.130634 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13398.710420 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13349.090780 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36876.900060 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 42672.221713 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39889.729495 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 12597.144817 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 12611.043361 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 12603.948842 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12236.533830 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12577.756654 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12394.678102 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 80500 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 80500 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23082.157511 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 26209.375227 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24666.266072 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21542.085648 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24325.170689 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22945.118773 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 1701384 # number of replacements -system.cpu0.icache.tags.tagsinuse 510.734068 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 113852033 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1701896 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 66.897174 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 25697074250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 399.197143 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 111.536926 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.779682 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.217846 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.997527 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 205 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 251 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 10 # Occupied blocks per task id -system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 117255837 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 117255837 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 57557381 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 56294652 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 113852033 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 57557381 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 56294652 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 113852033 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 57557381 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 56294652 # number of overall hits -system.cpu0.icache.overall_hits::total 113852033 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 856651 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 845251 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1701902 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 856651 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 845251 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1701902 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 856651 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 845251 # number of overall misses -system.cpu0.icache.overall_misses::total 1701902 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11730914498 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 11646451999 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 23377366497 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 11730914498 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 11646451999 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 23377366497 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 11730914498 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 11646451999 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 23377366497 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 58414032 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 57139903 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 115553935 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 58414032 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 57139903 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 115553935 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 58414032 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 57139903 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 115553935 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014665 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.014793 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014728 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014665 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.014793 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014728 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014665 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.014793 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014728 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13693.924945 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13778.690589 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13736.023870 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13693.924945 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13778.690589 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13736.023870 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13693.924945 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13778.690589 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13736.023870 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.fast_writes 0 # number of fast writes performed -system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 856651 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 845251 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1701902 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 856651 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 845251 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1701902 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 856651 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 845251 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1701902 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10442855002 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 10375133501 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 20817988503 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10442855002 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 10375133501 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 20817988503 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10442855002 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 10375133501 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 20817988503 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 677067750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 677067750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 677067750 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 677067750 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014665 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014793 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014728 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014665 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.014793 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.014728 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014665 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.014793 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.014728 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12190.326051 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12274.618428 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12232.189928 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12190.326051 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12274.618428 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12232.189928 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12190.326051 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12274.618428 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12232.189928 # average overall mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 6646 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 6646 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 1848 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 4797 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 1 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 6645 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 6645 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 6645 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 5540 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 12435.469314 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 10508.495094 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 6654.820556 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-8191 1371 24.75% 24.75% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::8192-16383 2761 49.84% 74.58% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-24575 1405 25.36% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::81920-90111 3 0.05% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 5540 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples -586099820 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 2.706592 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::gmean inf # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 1000233500 -170.66% -170.66% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::1 -1586333320 270.66% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total -586099820 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 3714 67.05% 67.05% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 1825 32.95% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 5539 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 6646 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 6646 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 5539 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5539 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 12185 # Table walker requests started/completed, data/inst -system.cpu1.dtb.inst_hits 0 # ITB inst hits -system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 12057381 # DTB read hits -system.cpu1.dtb.read_misses 5757 # DTB read misses -system.cpu1.dtb.write_hits 9774636 # DTB write hits -system.cpu1.dtb.write_misses 889 # DTB write misses -system.cpu1.dtb.flush_tlb 2932 # Number of times complete TLB was flushed -system.cpu1.dtb.flush_tlb_mva 421 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 4087 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 1001 # Number of TLB faults due to prefetch -system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 205 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 12063138 # DTB read accesses -system.cpu1.dtb.write_accesses 9775525 # DTB write accesses -system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 21832017 # DTB hits -system.cpu1.dtb.misses 6646 # DTB misses -system.cpu1.dtb.accesses 21838663 # DTB accesses -system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 3230 # Table walker walks requested -system.cpu1.itb.walker.walksShort 3230 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 673 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2557 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 3230 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 3230 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 3230 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 2426 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 12666.941467 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 10866.952957 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 6275.492791 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::2048-4095 541 22.30% 22.30% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::10240-12287 673 27.74% 50.04% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-14335 619 25.52% 75.56% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::20480-22527 528 21.76% 97.32% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::22528-24575 65 2.68% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 2426 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 1000198000 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 1000198000 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 1000198000 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 1753 72.26% 72.26% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 673 27.74% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 2426 # Table walker page sizes translated -system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 3230 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 3230 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2426 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2426 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 5656 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 57139903 # ITB inst hits -system.cpu1.itb.inst_misses 3230 # ITB inst misses -system.cpu1.itb.read_hits 0 # DTB read hits -system.cpu1.itb.read_misses 0 # DTB read misses -system.cpu1.itb.write_hits 0 # DTB write hits -system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 2932 # Number of times complete TLB was flushed -system.cpu1.itb.flush_tlb_mva 421 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2427 # Number of entries that have been flushed from TLB -system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu1.itb.read_accesses 0 # DTB read accesses -system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 57143133 # ITB inst accesses -system.cpu1.itb.hits 57139903 # DTB hits -system.cpu1.itb.misses 3230 # DTB misses -system.cpu1.itb.accesses 57143133 # DTB accesses -system.cpu1.numCycles 2903230224 # number of cpu cycles simulated -system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 55611529 # Number of instructions committed -system.cpu1.committedOps 67110942 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 59336824 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 5270 # Number of float alu accesses -system.cpu1.num_func_calls 4819801 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 7566653 # number of instructions that are conditional controls -system.cpu1.num_int_insts 59336824 # number of integer instructions -system.cpu1.num_fp_insts 5270 # number of float instructions -system.cpu1.num_int_register_reads 107900734 # number of times the integer registers were read -system.cpu1.num_int_register_writes 40745080 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 3840 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 1432 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 242074272 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 25879956 # number of times the CC registers were written -system.cpu1.num_mem_refs 22456627 # number of memory refs -system.cpu1.num_load_insts 12214155 # Number of load instructions -system.cpu1.num_store_insts 10242472 # Number of store instructions -system.cpu1.num_idle_cycles 2696428184.778518 # Number of idle cycles -system.cpu1.num_busy_cycles 206802039.221482 # Number of busy cycles -system.cpu1.not_idle_fraction 0.071232 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.928768 # Percentage of idle cycles -system.cpu1.Branches 12781357 # Number of branches fetched -system.cpu1.op_class::No_OpClass 130 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 46119057 67.20% 67.20% # Class of executed instruction -system.cpu1.op_class::IntMult 54779 0.08% 67.28% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 67.28% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 67.28% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 67.28% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 67.28% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 67.28% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 67.28% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 67.28% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 67.28% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 67.28% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 67.28% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 67.28% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 67.28% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 67.28% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 67.28% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 67.28% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 67.28% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 67.28% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 67.28% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 67.28% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 67.28% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 67.28% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 67.28% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 67.28% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 4036 0.01% 67.28% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 67.28% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 67.28% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 67.28% # Class of executed instruction -system.cpu1.op_class::MemRead 12214155 17.80% 85.08% # Class of executed instruction -system.cpu1.op_class::MemWrite 10242472 14.92% 100.00% # Class of executed instruction -system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 68634629 # Class of executed instruction -system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.iobus.trans_dist::ReadReq 30183 # Transaction distribution -system.iobus.trans_dist::ReadResp 30183 # Transaction distribution -system.iobus.trans_dist::WriteReq 59014 # Transaction distribution -system.iobus.trans_dist::WriteResp 22790 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72916 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72916 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 178394 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2480229 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 38469000 # Layer occupancy (ticks) -system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks) -system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) -system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) -system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) -system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks) -system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) -system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks) -system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) -system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) -system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) -system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) -system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) -system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 198848287 # Layer occupancy (ticks) -system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) -system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) -system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36807005 # Layer occupancy (ticks) -system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 36424 # number of replacements -system.iocache.tags.tagsinuse 1.134606 # Cycle average of tags in use -system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 299121172000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.134606 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.070913 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.070913 # Average percentage of cache occupancy -system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id -system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id -system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328122 # Number of tag accesses -system.iocache.tags.data_accesses 328122 # Number of data accesses -system.iocache.ReadReq_misses::realview.ide 234 # number of ReadReq misses -system.iocache.ReadReq_misses::total 234 # number of ReadReq misses -system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses -system.iocache.demand_misses::realview.ide 234 # number of demand (read+write) misses -system.iocache.demand_misses::total 234 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 234 # number of overall misses -system.iocache.overall_misses::total 234 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 29267377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 29267377 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6633096905 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 6633096905 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ide 29267377 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 29267377 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 29267377 # number of overall miss cycles -system.iocache.overall_miss_latency::total 29267377 # number of overall miss cycles -system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 234 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 234 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 234 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 234 # number of overall (read+write) accesses -system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses -system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses -system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses -system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses -system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses -system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 125074.260684 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 125074.260684 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183113.320036 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 183113.320036 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 125074.260684 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 125074.260684 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 125074.260684 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 125074.260684 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 22198 # number of cycles access was blocked -system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3387 # number of cycles access was blocked -system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6.553882 # average number of cycles each access was blocked -system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 0 # number of fast writes performed -system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 36190 # number of writebacks -system.iocache.writebacks::total 36190 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 234 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 234 # number of ReadReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 36224 # number of WriteInvalidateReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::total 36224 # number of WriteInvalidateReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 234 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 234 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 234 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 234 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 16965377 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 16965377 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4749438915 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4749438915 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 16965377 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 16965377 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 16965377 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 16965377 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72501.611111 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 72501.611111 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131113.044252 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131113.044252 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 72501.611111 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 72501.611111 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 72501.611111 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 72501.611111 # average overall mshr miss latency -system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 86345 # number of replacements -system.l2c.tags.tagsinuse 64916.534496 # Cycle average of tags in use -system.l2c.tags.total_refs 2772933 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 151598 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 18.291356 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 50295.187878 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.860187 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.965052 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4502.634002 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2814.628972 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 1.894234 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 5158.115832 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2140.248339 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.767444 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000044 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.068705 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.042948 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000029 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.078707 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.032658 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.990548 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65248 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 12 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 27 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2139 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6724 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 56346 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.995605 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 26318997 # Number of tag accesses -system.l2c.tags.data_accesses 26318997 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 6505 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 3514 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 848098 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 260151 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 6217 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 3258 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 835810 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 254237 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2217790 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 687030 # number of Writeback hits -system.l2c.Writeback_hits::total 687030 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 16 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 13 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 29 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 87471 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 80339 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 167810 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 6505 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 3514 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 848098 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 347622 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 6217 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 3258 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 835810 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 334576 # number of demand (read+write) hits -system.l2c.demand_hits::total 2385600 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 6505 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 3514 # number of overall hits -system.l2c.overall_hits::cpu0.inst 848098 # number of overall hits -system.l2c.overall_hits::cpu0.data 347622 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 6217 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 3258 # number of overall hits -system.l2c.overall_hits::cpu1.inst 835810 # number of overall hits -system.l2c.overall_hits::cpu1.data 334576 # number of overall hits -system.l2c.overall_hits::total 2385600 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 3 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 8541 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 5976 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 4 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 9421 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 6147 # number of ReadReq misses -system.l2c.ReadReq_misses::total 30094 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 1338 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1365 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2703 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 2 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 54481 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 73452 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 127933 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 3 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 8541 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 60457 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 4 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 9421 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 79599 # number of demand (read+write) misses -system.l2c.demand_misses::total 158027 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 3 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 8541 # number of overall misses -system.l2c.overall_misses::cpu0.data 60457 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 4 # number of overall misses -system.l2c.overall_misses::cpu1.inst 9421 # number of overall misses -system.l2c.overall_misses::cpu1.data 79599 # number of overall misses -system.l2c.overall_misses::total 158027 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 261750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 166000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 681157002 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 494631258 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 330000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 753847500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 510531136 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 2440924646 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 341989 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 434486 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 776475 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 159000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 159000 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 4180870378 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 5579789336 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 9760659714 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 261750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 166000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 681157002 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 4675501636 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 330000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 753847500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 6090320472 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 12201584360 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 261750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 166000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 681157002 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 4675501636 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 330000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 753847500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 6090320472 # number of overall miss cycles -system.l2c.overall_miss_latency::total 12201584360 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 6508 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 3516 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 856639 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 266127 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 6221 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 3258 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 845231 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 260384 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2247884 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 687030 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 687030 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 1354 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 1378 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 2732 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 2 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 141952 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 153791 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 295743 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 6508 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 3516 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 856639 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 408079 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 6221 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 3258 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 845231 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 414175 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2543627 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 6508 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 3516 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 856639 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 408079 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 6221 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 3258 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 845231 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 414175 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2543627 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000461 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000569 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.009970 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.022455 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000643 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.011146 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.023607 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.013388 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.988183 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.990566 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.989385 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.383799 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.477609 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.432582 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000461 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000569 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.009970 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.148150 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000643 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.011146 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.192187 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.062127 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000461 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000569 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.009970 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.148150 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000643 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.011146 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.192187 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.062127 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 87250 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 83000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 79751.434492 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 82769.621486 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 82500 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 80017.779429 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 83053.706849 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 81110.010168 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 255.597160 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 318.304762 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 287.264151 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 79500 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 79500 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 76739.971329 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 75965.111039 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 76295.089727 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 87250 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 83000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 79751.434492 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 77335.984849 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 82500 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 80017.779429 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 76512.524931 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 77212.023009 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 87250 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 83000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 79751.434492 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 77335.984849 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 82500 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 80017.779429 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 76512.524931 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 77212.023009 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.fast_writes 0 # number of fast writes performed -system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 79977 # number of writebacks -system.l2c.writebacks::total 79977 # number of writebacks -system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 3 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 8541 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 5976 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 4 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 9421 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 6147 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 30094 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 1338 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 1365 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 2703 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 2 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 54481 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 73452 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 127933 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 3 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 8541 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 60457 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 4 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 9421 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 79599 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 158027 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 3 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 8541 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 60457 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 4 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 9421 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 79599 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 158027 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 223750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 141000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 574142498 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 419922242 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 280000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 635806000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 433639364 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 2064154854 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 23826338 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 24325865 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 48152203 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 135000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 135000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3498745622 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4660357664 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 8159103286 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 223750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 141000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 574142498 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 3918667864 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 280000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 635806000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 5093997028 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 10223258140 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 223750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 141000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 574142498 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 3918667864 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 280000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 635806000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 5093997028 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 10223258140 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 546237750 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2603822250 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2793047000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 5943107000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2054472000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 2099890500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 4154362500 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 546237750 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 4658294250 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 4892937500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 10097469500 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000461 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000569 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.009970 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.022455 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000643 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.011146 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.023607 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.013388 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.988183 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.990566 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.989385 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.383799 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.477609 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.432582 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000461 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000569 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.009970 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.148150 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000643 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011146 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.192187 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.062127 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000461 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000569 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.009970 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.148150 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000643 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011146 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.192187 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.062127 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 74583.333333 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 70500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 67221.929282 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 70268.112784 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 70000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 67488.164738 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 70544.877827 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 68590.245697 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17807.427504 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17821.146520 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17814.355531 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 67500 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 67500 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 64219.555845 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 63447.661929 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 63776.377369 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 74583.333333 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 70500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 67221.929282 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 64817.438245 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 70000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 67488.164738 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 63995.741504 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 64693.110291 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 74583.333333 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 70500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 67221.929282 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 64817.438245 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 70000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 67488.164738 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 63995.741504 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 64693.110291 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 70492 # Transaction distribution -system.membus.trans_dist::ReadResp 70492 # Transaction distribution -system.membus.trans_dist::WriteReq 27594 # Transaction distribution -system.membus.trans_dist::WriteResp 27594 # Transaction distribution -system.membus.trans_dist::Writeback 116167 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4489 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4491 # Transaction distribution -system.membus.trans_dist::ReadExReq 126147 # Transaction distribution -system.membus.trans_dist::ReadExResp 126147 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2122 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 429068 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 536678 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108887 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 108887 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 645565 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4244 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 15156092 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 15319481 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 19954937 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 498 # Total snoops (count) -system.membus.snoop_fanout::samples 313389 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 313389 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 313389 # Request fanout histogram -system.membus.reqLayer0.occupancy 90494500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks) -system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1721500 # Layer occupancy (ticks) -system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 960656101 # Layer occupancy (ticks) -system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 947025657 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 37465995 # Layer occupancy (ticks) -system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA -system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA -system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU -system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post -system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR -system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU -system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post -system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR -system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU -system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post -system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR -system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU -system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post -system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR -system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU -system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post -system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR -system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU -system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post -system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR -system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU -system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post -system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU -system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post -system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR -system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post -system.realview.ethernet.postedInterrupts 0 # number of posts to CPU -system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 2303937 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2303837 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 27594 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 27594 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 687030 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 36246 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2732 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2734 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 295743 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 295743 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3421816 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2454612 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 18880 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 35749 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5931057 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 108955768 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96785921 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 27096 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 50916 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 205819701 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 52269 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3285526 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 3.011103 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.104785 # Request fanout histogram -system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 3249046 98.89% 98.89% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 36480 1.11% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3285526 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 2359229000 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 201000 # Layer occupancy (ticks) -system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2567253247 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1309775845 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 12106000 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 23020250 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) - ----------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/system.terminal deleted file mode 100644 index b3be0ec54..000000000 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/system.terminal +++ /dev/null @@ -1,208 +0,0 @@ -Booting Linux on physical CPU 0x0 - Initializing cgroup subsys cpuset - Linux version 3.13.0-rc2 (tony@vamp) (gcc version 4.8.2 (Ubuntu/Linaro 4.8.2-16ubuntu4) ) #1 SMP PREEMPT Mon Oct 13 15:09:23 EDT 2014 - Kernel was built at commit id '' - CPU: ARMv7 Processor [410fc0f0] revision 0 (ARMv7), cr=10c53c7d - CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache - Machine model: V2P-CA15 - bootconsole [earlycon0] enabled - Memory policy: Data cache writealloc - kdebugv2m: Following are test values to confirm proper working - kdebugv2m: Ranges 42000000 0 - kdebugv2m: Regs 30000000 1000000 - kdebugv2m: Virtual-Reg f0000000 - kdebugv2m: pci node addr_cells 3 - kdebugv2m: pci node size_cells 2 - kdebugv2m: motherboard addr_cells 2 - On node 0 totalpages: 65536 - free_area_init_node: node 0, pgdat 8072dcc0, node_mem_map 8078f000 - Normal zone: 512 pages used for memmap - Normal zone: 0 pages reserved - Normal zone: 65536 pages, LIFO batch:15 - sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 178956969942ns - PERCPU: Embedded 8 pages/cpu @80996000 s11648 r8192 d12928 u32768 - pcpu-alloc: s11648 r8192 d12928 u32768 alloc=8*4096 - pcpu-alloc: [0] 0 - Built 1 zonelists in Zone order, mobility grouping on. Total pages: 65024 - Kernel command line: earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 - PID hash table entries: 1024 (order: 0, 4096 bytes) - Dentry cache hash table entries: 32768 (order: 5, 131072 bytes) - Inode-cache hash table entries: 16384 (order: 4, 65536 bytes) - Memory: 235688K/262144K available (5248K kernel code, 249K rwdata, 1540K rodata, 295K init, 368K bss, 26456K reserved, 0K highmem) - Virtual kernel memory layout: - vector : 0xffff0000 - 0xffff1000 ( 4 kB) - fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB) - vmalloc : 0x90800000 - 0xff000000 (1768 MB) - lowmem : 0x80000000 - 0x90000000 ( 256 MB) - pkmap : 0x7fe00000 - 0x80000000 ( 2 MB) - modules : 0x7f000000 - 0x7fe00000 ( 14 MB) - .text : 0x80008000 - 0x806a942c (6790 kB) - .init : 0x806aa000 - 0x806f3d80 ( 296 kB) - .data : 0x806f4000 - 0x80732754 ( 250 kB) - .bss : 0x80732754 - 0x8078e9d8 ( 369 kB) - SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1 - Preemptible hierarchical RCU implementation. - RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=1. - NR_IRQS:16 nr_irqs:16 16 - Architected cp15 timer(s) running at 25.16MHz (phys). - sched_clock: 56 bits at 25MHz, resolution 39ns, wraps every 2730666655744ns - Switching to timer-based delay loop - Console: colour dummy device 80x30 - Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480) - pid_max: default: 32768 minimum: 301 - Mount-cache hash table entries: 512 - CPU: Testing write buffer coherency: ok - CPU0: update cpu_power 1024 - CPU0: thread -1, cpu 0, socket 0, mpidr 80000000 - Setting up static identity map for 0x804fee68 - 0x804fee9c - Brought up 1 CPUs - SMP: Total of 1 processors activated. - CPU: All CPU(s) started in SVC mode. - VFP support v0.3: implementor 41 architecture 4 part 30 variant a rev 0 - NET: Registered protocol family 16 - DMA: preallocated 256 KiB pool for atomic coherent allocations - of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000 - of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/aaci@040000 - of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/mmci@050000 - of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000 - of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000 - of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000 - of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000 - hw-breakpoint: Debug register access (0xee113e93) caused undefined instruction on CPU 0 - hw-breakpoint: Debug register access (0xee013e90) caused undefined instruction on CPU 0 - hw-breakpoint: Debug register access (0xee003e17) caused undefined instruction on CPU 0 - hw-breakpoint: CPU 0 failed to disable vector catch - Serial: AMBA PL011 UART driver - 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3 - console [ttyAMA0] enabled -console [ttyAMA0] enabled - bootconsole [earlycon0] disabled -bootconsole [earlycon0] disabled - PCI host bridge to bus 0000:00 -pci_bus 0000:00: root bus resource [io 0x0000-0xffffffff] -pci_bus 0000:00: root bus resource [mem 0x00000000-0xffffffff] -pci_bus 0000:00: root bus resource [bus 00-ff] -pci 0000:00:00.0: [8086:1075] type 00 class 0x020000 -pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff] -pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref] -pci 0000:00:01.0: [8086:7111] type 00 class 0x010185 -pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007] -pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003] -pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007] -pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003] -pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f] -pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref] -PCI: bus0: Fast back to back transfers disabled -pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff] -pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref] -pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref] -pci 0000:00:01.0: BAR 4: assigned [io 0x2f000000-0x2f00000f] -pci 0000:00:01.0: BAR 0: assigned [io 0x2f000010-0x2f000017] -pci 0000:00:01.0: BAR 2: assigned [io 0x2f000018-0x2f00001f] -pci 0000:00:01.0: BAR 1: assigned [io 0x2f000020-0x2f000023] -pci 0000:00:01.0: BAR 3: assigned [io 0x2f000024-0x2f000027] -pci_bus 0000:00: resource 4 [io 0x0000-0xffffffff] -pci_bus 0000:00: resource 5 [mem 0x00000000-0xffffffff] -PCI map irq: slot 0, pin 1, devslot 0, irq: 68 -PCI map irq: slot 1, pin 2, devslot 1, irq: 69 -bio: create slab at 0 -vgaarb: loaded -SCSI subsystem initialized -libata version 3.00 loaded. -usbcore: registered new interface driver usbfs -usbcore: registered new interface driver hub -usbcore: registered new device driver usb -pps_core: LinuxPPS API ver. 1 registered -pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti -PTP clock support registered -Advanced Linux Sound Architecture Driver Initialized. -Switched to clocksource arch_sys_counter -NET: Registered protocol family 2 -TCP established hash table entries: 2048 (order: 1, 8192 bytes) -TCP bind hash table entries: 2048 (order: 2, 16384 bytes) -TCP: Hash tables configured (established 2048 bind 2048) -TCP: reno registered -UDP hash table entries: 256 (order: 1, 8192 bytes) -UDP-Lite hash table entries: 256 (order: 1, 8192 bytes) -NET: Registered protocol family 1 -RPC: Registered named UNIX socket transport module. -RPC: Registered udp transport module. -RPC: Registered tcp transport module. -RPC: Registered tcp NFSv4.1 backchannel transport module. -PCI: CLS 64 bytes, default 64 -hw perfevents: enabled with ARMv7_Cortex_A15 PMU driver, 1 counters available -jffs2: version 2.2. (NAND) © 2001-2006 Red Hat, Inc. -msgmni has been set to 460 -io scheduler noop registered (default) -brd: module loaded -loop: module loaded -ata_piix 0000:00:01.0: version 2.13 -PCI: enabling device 0000:00:01.0 (0040 -> 0041) -scsi0 : ata_piix -scsi1 : ata_piix -ata1: PATA max UDMA/33 cmd 0x2f000010 ctl 0x2f000020 bmdma 0x2f000000 irq 69 -ata2: PATA max UDMA/33 cmd 0x2f000018 ctl 0x2f000024 bmdma 0x2f000008 irq 69 -e100: Intel(R) PRO/100 Network Driver, 3.5.24-k2-NAPI -e100: Copyright(c) 1999-2006 Intel Corporation -e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI -e1000: Copyright (c) 1999-2006 Intel Corporation. -PCI: enabling device 0000:00:00.0 (0040 -> 0042) -ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66 -ata1.00: 1048320 sectors, multi 0: LBA -ata1.00: configured for UDMA/33 -scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5 -sd 0:0:0:0: [sda] 1048320 512-byte logical blocks: (536 MB/511 MiB) -sd 0:0:0:0: [sda] Write Protect is off -sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00 -sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA - sda: sda1 -sd 0:0:0:0: Attached scsi generic sg0 type 0 -sd 0:0:0:0: [sda] Attached SCSI disk -e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01 -e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection -e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k -e1000e: Copyright(c) 1999 - 2013 Intel Corporation. -igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k -igb: Copyright (c) 2007-2013 Intel Corporation. -igbvf: Intel(R) Gigabit Virtual Function Network Driver - version 2.0.2-k -igbvf: Copyright (c) 2009 - 2012 Intel Corporation. -ixgbe: Intel(R) 10 Gigabit PCI Express Network Driver - version 3.15.1-k -ixgbe: Copyright (c) 1999-2013 Intel Corporation. -ixgbevf: Intel(R) 10 Gigabit PCI Express Virtual Function Network Driver - version 2.11.3-k -ixgbevf: Copyright (c) 2009 - 2012 Intel Corporation. -ixgb: Intel(R) PRO/10GbE Network Driver - version 1.0.135-k2-NAPI -ixgb: Copyright (c) 1999-2008 Intel Corporation. -smsc911x: Driver version 2008-10-21 -smsc911x 1a000000.ethernet (unregistered net_device): couldn't get clock -2 -nxp-isp1760 1b000000.usb: NXP ISP1760 USB Host Controller -nxp-isp1760 1b000000.usb: new USB bus registered, assigned bus number 1 -nxp-isp1760 1b000000.usb: Scratch test failed. -nxp-isp1760 1b000000.usb: can't setup: -19 -nxp-isp1760 1b000000.usb: USB bus 1 deregistered -usbcore: registered new interface driver usb-storage -mousedev: PS/2 mouse device common for all mice -rtc-pl031 1c170000.rtc: rtc core: registered pl031 as rtc0 -usbcore: registered new interface driver usbhid -usbhid: USB HID core driver -ashmem: initialized -logger: created 256K log 'log_main' -logger: created 256K log 'log_events' -logger: created 256K log 'log_radio' -logger: created 256K log 'log_system' -oprofile: using timer interrupt. -TCP: cubic registered -NET: Registered protocol family 10 -NET: Registered protocol family 17 -rtc-pl031 1c170000.rtc: setting system clock to 2009-01-01 12:00:00 UTC (1230811200) -ALSA device list: - No soundcards found. -input: AT Raw Set 2 keyboard as /devices/smb.14/motherboard.15/iofpga.17/1c060000.kmi/serio0/input/input0 -input: touchkitPS/2 eGalax Touchscreen as /devices/smb.14/motherboard.15/iofpga.17/1c070000.kmi/serio1/input/input2 -VFS: Mounted root (ext2 filesystem) on device 8:1. -Freeing unused kernel memory: 292K (806aa000 - 806f3000) - init started: BusyBox v1.15.3 (2010-05-07 01:27:07 BST) - starting pid 673, tty '': '/etc/rc.d/rc.local' -warning: can't open /etc/mtab: No such file or directory -Thu Jan 1 12:00:02 UTC 2009 -S: devpts -Thu Jan 1 12:00:02 UTC 2009 diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/chair.cook.ppm b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/chair.cook.ppm deleted file mode 100644 index 9ac19076f..000000000 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/chair.cook.ppm +++ /dev/null @@ -1,4 +0,0 @@ -P6 -15 15 -255 -   !!!  !!!$$$&&&'''&&&%%% !!!%%%(((******)))(((!!!###'''***+++,,,+++)))"""###''')))++++++***)))!!!!!!%%%((()))))))))''' """%%%&&&'''&&&%%%%%%  !!!"""#########"""(((---222666&&&...///===;;;999555111,,,((($$$DDDKKKRRRXXXBBB†††‘‘‘jjjWWWZZZUUUNNNGGG???888[[[dddkkkrrr]]]CCC===eeeaaarrrkkkddd[[[SSSKKKiiipppvvvvvvEEEggg{{{uuunnnfff^^^VVVmmmsssxxx|||oooEEEDDD]]]vvvzzzuuuooohhhaaaZZZjjjooossswwwyyyzzzzzzyyywwwtttoookkkeee```ZZZeeeiiilllnnnpppppppppooonnnkkkhhhddd```\\\WWW \ No newline at end of file diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini deleted file mode 100644 index 392920ac8..000000000 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini +++ /dev/null @@ -1,270 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -eventq_index=0 -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=atomic -mem_ranges= -memories=system.physmem -num_work_ids=16 -readfile= -symbolfile= -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=AtomicSimpleCPU -children=dstage2_mmu dtb interrupts isa istage2_mmu itb tracer workload -branchPred=Null -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dstage2_mmu=system.cpu.dstage2_mmu -dtb=system.cpu.dtb -eventq_index=0 -fastmem=false -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -istage2_mmu=system.cpu.istage2_mmu -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -profile=0 -progress_interval=0 -simpoint_start_insts= -simulate_data_stalls=false -simulate_inst_stalls=false -socket_id=0 -switched_out=false -system=system -tracer=system.cpu.tracer -width=1 -workload=system.cpu.workload -dcache_port=system.membus.slave[2] -icache_port=system.membus.slave[1] - -[system.cpu.dstage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb -tlb=system.cpu.dtb - -[system.cpu.dstage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -walker=system.cpu.dstage2_mmu.stage2_tlb.walker - -[system.cpu.dstage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -sys=system -port=system.membus.slave[6] - -[system.cpu.dtb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -walker=system.cpu.dtb.walker - -[system.cpu.dtb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -sys=system -port=system.membus.slave[4] - -[system.cpu.interrupts] -type=ArmInterrupts -eventq_index=0 - -[system.cpu.isa] -type=ArmISA -eventq_index=0 -fpsid=1090793632 -id_aa64afr0_el1=0 -id_aa64afr1_el1=0 -id_aa64dfr0_el1=1052678 -id_aa64dfr1_el1=0 -id_aa64isar0_el1=0 -id_aa64isar1_el1=0 -id_aa64mmfr0_el1=15728642 -id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=17 -id_aa64pfr1_el1=0 -id_isar0=34607377 -id_isar1=34677009 -id_isar2=555950401 -id_isar3=17899825 -id_isar4=268501314 -id_isar5=0 -id_mmfr0=270536963 -id_mmfr1=0 -id_mmfr2=19070976 -id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 -midr=1091551472 -system=system - -[system.cpu.istage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu.istage2_mmu.stage2_tlb -tlb=system.cpu.itb - -[system.cpu.istage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -walker=system.cpu.istage2_mmu.stage2_tlb.walker - -[system.cpu.istage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -sys=system -port=system.membus.slave[5] - -[system.cpu.itb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -walker=system.cpu.itb.walker - -[system.cpu.itb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -sys=system -port=system.membus.slave[3] - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=mcf mcf.in -cwd=build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/mcf -gid=100 -input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=55300000000 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -clk_domain=system.clk_domain -eventq_index=0 -header_cycles=1 -snoop_filter=Null -system=system -use_default_range=false -width=8 -master=system.physmem.port -slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port - -[system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=true -eventq_index=0 -in_addr_map=true -latency=30000 -latency_var=0 -null=false -range=0:268435455 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/mcf.out b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/mcf.out deleted file mode 100644 index 095132477..000000000 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/mcf.out +++ /dev/null @@ -1,999 +0,0 @@ -() -500 -() -499 -() -498 -() -496 -() -495 -() -494 -() -493 -() -492 -() -491 -() -490 -() -489 -() -488 -() -487 -() -486 -() -484 -() -482 -() -481 -() -480 -() -479 -() -478 -() -477 -() -476 -() -475 -() -474 -() -473 -() -472 -() -471 -() -469 -() -468 -() -467 -() -466 -() -465 -() -464 -() -463 -() -462 -() -461 -() -460 -() -459 -() -458 -() -457 -() -455 -() -454 -() -452 -() -451 -() -450 -() -449 -() -448 -() -446 -() -445 -() -444 -() -443 -() -442 -() -440 -() -439 -() -438 -() -436 -() -435 -() -433 -() -432 -() -431 -() -428 -() -427 -() -425 -() -424 -() -423 -() -420 -() -419 -() -416 -() -414 -() -413 -() -412 -() -407 -() -406 -() -405 -() -404 -() -403 -() -402 -() -401 -() -400 -() -399 -() -398 -() -396 -() -395 -() -393 -() -392 -() -390 -() -389 -() -388 -() -387 -() -386 -() -385 -() -384 -() -383 -() -382 -() -381 -() -380 -() -379 -() -377 -() -375 -() -374 -() -373 -() -372 -() -371 -() -370 -() -369 -() -368 -() -366 -() -365 -() -364 -() -362 -() -361 -() -360 -() -359 -() -358 -() -357 -() -356 -() -355 -() -354 -() -352 -() -350 -() -347 -() -344 -() -342 -() -341 -() -340 -() -339 -() -338 -() -332 -() -325 -() -320 -*** -345 -() -319 -*** -497 -() -318 -*** -349 -() -317 -*** -408 -() -316 -*** -324 -() -315 -*** -328 -() -314 -*** -335 -() -313 -*** -378 -() -312 -*** -426 -() -311 -*** -411 -() -304 -*** -343 -() -303 -*** -417 -() -302 -*** -485 -() -301 -*** -363 -() -300 -*** -376 -() -299 -*** -333 -() -292 -*** -337 -() -291 -*** -409 -() -290 -*** -421 -() -289 -*** -437 -() -288 -*** -430 -() -287 -*** -348 -() -286 -*** -326 -() -284 -() -282 -*** -308 -() -279 -*** -297 -*** -305 -() -278 -() -277 -*** -307 -() -276 -*** -296 -() -273 -() -271 -() -265 -() -246 -*** -267 -() -245 -*** -280 -() -244 -*** -391 -() -243 -*** -330 -() -242 -*** -456 -() -241 -*** -346 -() -240 -*** -483 -() -239 -*** -260 -() -238 -*** -261 -() -237 -*** -262 -*** -294 -() -236 -*** -253 -() -229 -*** -397 -() -228 -*** -298 -() -227 -*** -415 -() -226 -*** -264 -() -224 -*** -232 -() -222 -*** -233 -() -217 -*** -250 -() -211 -*** -331 -() -210 -*** -394 -() -209 -*** -410 -() -208 -*** -321 -() -207 -*** -327 -() -206 -*** -309 -() -199 -*** -259 -() -198 -*** -219 -() -197 -*** -220 -() -195 -*** -429 -() -194 -*** -470 -() -193 -*** -274 -() -191 -*** -203 -() -190 -*** -263 -() -189 -215 -*** -230 -() -188 -*** -266 -*** -295 -() -182 -*** -329 -() -181 -*** -351 -() -180 -*** -441 -() -179 -*** -453 -() -178 -*** -418 -() -177 -*** -353 -() -176 -*** -422 -() -175 -*** -225 -*** -255 -() -174 -*** -269 -() -173 -*** -214 -() -172 -*** -186 -() -171 -*** -447 -() -170 -*** -270 -*** -306 -() -169 -*** -336 -() -168 -*** -285 -() -165 -*** -249 -() -146 -*** -154 -() -143 -*** -334 -() -142 -*** -216 -*** -257 -() -141 -*** -167 -*** -251 -() -140 -*** -162 -*** -293 -() -139 -*** -158 -() -137 -*** -166 -*** -201 -() -136 -*** -160 -() -134 -*** -221 -() -132 -*** -213 -() -131 -*** -187 -() -129 -*** -235 -() -128 -*** -153 -() -127 -*** -156 -() -126 -*** -159 -*** -218 -() -125 -*** -155 -() -124 -*** -157 -() -123 -*** -152 -() -116 -*** -135 -*** -163 -() -115 -*** -133 -*** -204 -*** -248 -() -114 -*** -192 -*** -212 -() -113 -*** -268 -() -112 -*** -367 -() -111 -*** -272 -() -110 -*** -434 -() -109 -*** -323 -() -108 -*** -281 -() -107 -*** -144 -*** -148 -() -106 -*** -275 -() -105 -*** -196 -*** -254 -() -104 -*** -138 -*** -161 -() -103 -*** -310 -() -102 -*** -223 -*** -252 -() -80 -() -70 -() -69 -() -68 -() -66 -() -64 -() -62 -*** -256 -() -61 -*** -93 -() -59 -*** -120 -() -58 -() -57 -*** -183 -() -55 -() -54 -() -52 -*** -147 -() -51 -*** -118 -() -50 -*** -83 -() -49 -*** -98 -() -48 -*** -99 -() -47 -() -46 -*** -184 -() -45 -*** -121 -() -44 -() -43 -*** -88 -() -42 -*** -122 -() -41 -*** -91 -() -40 -*** -96 -() -38 -*** -100 -() -37 -*** -149 -() -36 -*** -74 -() -35 -*** -258 -() -34 -*** -151 -() -33 -*** -85 -() -32 -() -31 -*** -94 -() -30 -*** -97 -() -29 -*** -90 -() -28 -*** -89 -() -27 -*** -92 -() -26 -*** -72 -*** -247 -() -25 -*** -86 -() -24 -*** -82 -() -23 -*** -87 -*** -117 -() -22 -*** -76 -*** -119 -() -21 -*** -84 -() -20 -*** -78 -() -19 -*** -73 -() -18 -*** -81 -() -17 -*** -65 -() -16 -*** -63 -*** -101 -() -15 -*** -71 -() -14 -*** -75 -() -13 -*** -322 -() -12 -*** -77 -() -11 -*** -283 -() -10 -*** -79 -() -9 -*** -145 -*** -150 -() -8 -*** -67 -() -7 -*** -60 -*** -231 -() -6 -*** -56 -*** -234 -() -5 -*** -164 -*** -202 -() -4 -*** -53 -() -3 -*** -130 -*** -185 -*** -200 -() -2 -*** -205 -() -1 -*** -39 -*** -95 diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simerr b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simerr deleted file mode 100755 index 1a4f96712..000000000 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simerr +++ /dev/null @@ -1 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout deleted file mode 100755 index c759bbe65..000000000 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout +++ /dev/null @@ -1,27 +0,0 @@ -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Jan 23 2014 12:08:08 -gem5 started Jan 23 2014 17:11:38 -gem5 executing on u200540-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic -Global frequency set at 1000000000000 ticks per second - 0: system.cpu.isa: ISA system set to: 0 0x63b66c0 -info: Entering event queue @ 0. Starting simulation... - -MCF SPEC version 1.6.I -by Andreas Loebel -Copyright (c) 1998,1999 ZIB Berlin -All Rights Reserved. - -nodes : 500 -active arcs : 1905 -simplex iterations : 1502 -flow value : 4990014995 -new implicit arcs : 23867 -active arcs : 25772 -simplex iterations : 2663 -flow value : 3080014995 -checksum : 68389 -optimal -Exiting @ tick 54240661000 because target called exit() diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt deleted file mode 100644 index b143a6790..000000000 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt +++ /dev/null @@ -1,245 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.054141 # Number of seconds simulated -sim_ticks 54141000000 # Number of ticks simulated -final_tick 54141000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1893120 # Simulator instruction rate (inst/s) -host_op_rate 1902548 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1131265211 # Simulator tick rate (ticks/s) -host_mem_usage 433636 # Number of bytes of host memory used -host_seconds 47.86 # Real time elapsed on the host -sim_insts 90602407 # Number of instructions simulated -sim_ops 91053638 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 431323080 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 90016598 # Number of bytes read from this memory -system.physmem.bytes_read::total 521339678 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 431323080 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 431323080 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 18908138 # Number of bytes written to this memory -system.physmem.bytes_written::total 18908138 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 107830770 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 22461532 # Number of read requests responded to by this memory -system.physmem.num_reads::total 130292302 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 4738868 # Number of write requests responded to by this memory -system.physmem.num_writes::total 4738868 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7966662603 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1662632718 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 9629295321 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7966662603 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7966662603 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 349238802 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 349238802 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7966662603 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2011871521 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 9978534124 # Total bandwidth to/from this memory (bytes/s) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 0 # Table walker walks requested -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 0 # Table walker walks requested -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 108282001 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 90602407 # Number of instructions committed -system.cpu.committedOps 91053638 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 72326352 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses -system.cpu.num_func_calls 112245 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 15520157 # number of instructions that are conditional controls -system.cpu.num_int_insts 72326352 # number of integer instructions -system.cpu.num_fp_insts 48 # number of float instructions -system.cpu.num_int_register_reads 124257699 # number of times the integer registers were read -system.cpu.num_int_register_writes 52782988 # number of times the integer registers were written -system.cpu.num_fp_register_reads 54 # number of times the floating registers were read -system.cpu.num_fp_register_writes 30 # number of times the floating registers were written -system.cpu.num_cc_register_reads 271814240 # number of times the CC registers were read -system.cpu.num_cc_register_writes 53956115 # number of times the CC registers were written -system.cpu.num_mem_refs 27220755 # number of memory refs -system.cpu.num_load_insts 22475911 # Number of load instructions -system.cpu.num_store_insts 4744844 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 108282000.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 18732304 # Number of branches fetched -system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 63822828 70.09% 70.09% # Class of executed instruction -system.cpu.op_class::IntMult 10474 0.01% 70.10% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 6 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 15 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 2 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::MemRead 22475911 24.68% 94.79% # Class of executed instruction -system.cpu.op_class::MemWrite 4744844 5.21% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 91054080 # Class of executed instruction -system.membus.trans_dist::ReadReq 130287905 # Transaction distribution -system.membus.trans_dist::ReadResp 130291792 # Transaction distribution -system.membus.trans_dist::WriteReq 4734981 # Transaction distribution -system.membus.trans_dist::WriteResp 4734981 # Transaction distribution -system.membus.trans_dist::SoftPFReq 510 # Transaction distribution -system.membus.trans_dist::SoftPFResp 510 # Transaction distribution -system.membus.trans_dist::LoadLockedReq 3887 # Transaction distribution -system.membus.trans_dist::StoreCondReq 3887 # Transaction distribution -system.membus.trans_dist::StoreCondResp 3887 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 215661540 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 54400800 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 270062340 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 431323080 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 108924736 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 540247816 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 135031170 # Request fanout histogram -system.membus.snoop_fanout::mean 2.798562 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.401074 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::2 27200400 20.14% 20.14% # Request fanout histogram -system.membus.snoop_fanout::3 107830770 79.86% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 2 # Request fanout histogram -system.membus.snoop_fanout::max_value 3 # Request fanout histogram -system.membus.snoop_fanout::total 135031170 # Request fanout histogram - ----------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/chair.cook.ppm b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/chair.cook.ppm deleted file mode 100644 index 9ac19076f..000000000 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/chair.cook.ppm +++ /dev/null @@ -1,4 +0,0 @@ -P6 -15 15 -255 -   !!!  !!!$$$&&&'''&&&%%% !!!%%%(((******)))(((!!!###'''***+++,,,+++)))"""###''')))++++++***)))!!!!!!%%%((()))))))))''' """%%%&&&'''&&&%%%%%%  !!!"""#########"""(((---222666&&&...///===;;;999555111,,,((($$$DDDKKKRRRXXXBBB†††‘‘‘jjjWWWZZZUUUNNNGGG???888[[[dddkkkrrr]]]CCC===eeeaaarrrkkkddd[[[SSSKKKiiipppvvvvvvEEEggg{{{uuunnnfff^^^VVVmmmsssxxx|||oooEEEDDD]]]vvvzzzuuuooohhhaaaZZZjjjooossswwwyyyzzzzzzyyywwwtttoookkkeee```ZZZeeeiiilllnnnpppppppppooonnnkkkhhhddd```\\\WWW \ No newline at end of file diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini deleted file mode 100644 index e662df1f5..000000000 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini +++ /dev/null @@ -1,383 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -eventq_index=0 -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges= -memories=system.physmem -num_work_ids=16 -readfile= -symbolfile= -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=TimingSimpleCPU -children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload -branchPred=Null -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dstage2_mmu=system.cpu.dstage2_mmu -dtb=system.cpu.dtb -eventq_index=0 -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -istage2_mmu=system.cpu.istage2_mmu -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -switched_out=false -system=system -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.dcache] -type=BaseCache -children=tags -addr_ranges=0:18446744073709551615 -assoc=2 -clk_domain=system.cpu_clk_domain -eventq_index=0 -forward_snoops=true -hit_latency=2 -is_top_level=true -max_miss_count=0 -mshrs=4 -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=262144 -system=system -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dcache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -eventq_index=0 -hit_latency=2 -sequential_access=false -size=262144 - -[system.cpu.dstage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb -tlb=system.cpu.dtb - -[system.cpu.dstage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -walker=system.cpu.dstage2_mmu.stage2_tlb.walker - -[system.cpu.dstage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -sys=system -port=system.cpu.toL2Bus.slave[5] - -[system.cpu.dtb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -walker=system.cpu.dtb.walker - -[system.cpu.dtb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -sys=system -port=system.cpu.toL2Bus.slave[3] - -[system.cpu.icache] -type=BaseCache -children=tags -addr_ranges=0:18446744073709551615 -assoc=2 -clk_domain=system.cpu_clk_domain -eventq_index=0 -forward_snoops=true -hit_latency=2 -is_top_level=true -max_miss_count=0 -mshrs=4 -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=131072 -system=system -tags=system.cpu.icache.tags -tgts_per_mshr=20 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.icache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -eventq_index=0 -hit_latency=2 -sequential_access=false -size=131072 - -[system.cpu.interrupts] -type=ArmInterrupts -eventq_index=0 - -[system.cpu.isa] -type=ArmISA -eventq_index=0 -fpsid=1090793632 -id_aa64afr0_el1=0 -id_aa64afr1_el1=0 -id_aa64dfr0_el1=1052678 -id_aa64dfr1_el1=0 -id_aa64isar0_el1=0 -id_aa64isar1_el1=0 -id_aa64mmfr0_el1=15728642 -id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=17 -id_aa64pfr1_el1=0 -id_isar0=34607377 -id_isar1=34677009 -id_isar2=555950401 -id_isar3=17899825 -id_isar4=268501314 -id_isar5=0 -id_mmfr0=270536963 -id_mmfr1=0 -id_mmfr2=19070976 -id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 -midr=1091551472 -system=system - -[system.cpu.istage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu.istage2_mmu.stage2_tlb -tlb=system.cpu.itb - -[system.cpu.istage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -walker=system.cpu.istage2_mmu.stage2_tlb.walker - -[system.cpu.istage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -sys=system -port=system.cpu.toL2Bus.slave[4] - -[system.cpu.itb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -walker=system.cpu.itb.walker - -[system.cpu.itb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -sys=system -port=system.cpu.toL2Bus.slave[2] - -[system.cpu.l2cache] -type=BaseCache -children=tags -addr_ranges=0:18446744073709551615 -assoc=8 -clk_domain=system.cpu_clk_domain -eventq_index=0 -forward_snoops=true -hit_latency=20 -is_top_level=false -max_miss_count=0 -mshrs=20 -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=2097152 -system=system -tags=system.cpu.l2cache.tags -tgts_per_mshr=12 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.cpu.l2cache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -eventq_index=0 -hit_latency=20 -sequential_access=false -size=2097152 - -[system.cpu.toL2Bus] -type=CoherentXBar -clk_domain=system.cpu_clk_domain -eventq_index=0 -header_cycles=1 -snoop_filter=Null -system=system -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=mcf mcf.in -cwd=build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-timing -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/mcf -gid=100 -input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=55300000000 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -clk_domain=system.clk_domain -eventq_index=0 -header_cycles=1 -snoop_filter=Null -system=system -use_default_range=false -width=8 -master=system.physmem.port -slave=system.system_port system.cpu.l2cache.mem_side - -[system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=true -eventq_index=0 -in_addr_map=true -latency=30000 -latency_var=0 -null=false -range=0:268435455 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/mcf.out b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/mcf.out deleted file mode 100644 index 095132477..000000000 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/mcf.out +++ /dev/null @@ -1,999 +0,0 @@ -() -500 -() -499 -() -498 -() -496 -() -495 -() -494 -() -493 -() -492 -() -491 -() -490 -() -489 -() -488 -() -487 -() -486 -() -484 -() -482 -() -481 -() -480 -() -479 -() -478 -() -477 -() -476 -() -475 -() -474 -() -473 -() -472 -() -471 -() -469 -() -468 -() -467 -() -466 -() -465 -() -464 -() -463 -() -462 -() -461 -() -460 -() -459 -() -458 -() -457 -() -455 -() -454 -() -452 -() -451 -() -450 -() -449 -() -448 -() -446 -() -445 -() -444 -() -443 -() -442 -() -440 -() -439 -() -438 -() -436 -() -435 -() -433 -() -432 -() -431 -() -428 -() -427 -() -425 -() -424 -() -423 -() -420 -() -419 -() -416 -() -414 -() -413 -() -412 -() -407 -() -406 -() -405 -() -404 -() -403 -() -402 -() -401 -() -400 -() -399 -() -398 -() -396 -() -395 -() -393 -() -392 -() -390 -() -389 -() -388 -() -387 -() -386 -() -385 -() -384 -() -383 -() -382 -() -381 -() -380 -() -379 -() -377 -() -375 -() -374 -() -373 -() -372 -() -371 -() -370 -() -369 -() -368 -() -366 -() -365 -() -364 -() -362 -() -361 -() -360 -() -359 -() -358 -() -357 -() -356 -() -355 -() -354 -() -352 -() -350 -() -347 -() -344 -() -342 -() -341 -() -340 -() -339 -() -338 -() -332 -() -325 -() -320 -*** -345 -() -319 -*** -497 -() -318 -*** -349 -() -317 -*** -408 -() -316 -*** -324 -() -315 -*** -328 -() -314 -*** -335 -() -313 -*** -378 -() -312 -*** -426 -() -311 -*** -411 -() -304 -*** -343 -() -303 -*** -417 -() -302 -*** -485 -() -301 -*** -363 -() -300 -*** -376 -() -299 -*** -333 -() -292 -*** -337 -() -291 -*** -409 -() -290 -*** -421 -() -289 -*** -437 -() -288 -*** -430 -() -287 -*** -348 -() -286 -*** -326 -() -284 -() -282 -*** -308 -() -279 -*** -297 -*** -305 -() -278 -() -277 -*** -307 -() -276 -*** -296 -() -273 -() -271 -() -265 -() -246 -*** -267 -() -245 -*** -280 -() -244 -*** -391 -() -243 -*** -330 -() -242 -*** -456 -() -241 -*** -346 -() -240 -*** -483 -() -239 -*** -260 -() -238 -*** -261 -() -237 -*** -262 -*** -294 -() -236 -*** -253 -() -229 -*** -397 -() -228 -*** -298 -() -227 -*** -415 -() -226 -*** -264 -() -224 -*** -232 -() -222 -*** -233 -() -217 -*** -250 -() -211 -*** -331 -() -210 -*** -394 -() -209 -*** -410 -() -208 -*** -321 -() -207 -*** -327 -() -206 -*** -309 -() -199 -*** -259 -() -198 -*** -219 -() -197 -*** -220 -() -195 -*** -429 -() -194 -*** -470 -() -193 -*** -274 -() -191 -*** -203 -() -190 -*** -263 -() -189 -215 -*** -230 -() -188 -*** -266 -*** -295 -() -182 -*** -329 -() -181 -*** -351 -() -180 -*** -441 -() -179 -*** -453 -() -178 -*** -418 -() -177 -*** -353 -() -176 -*** -422 -() -175 -*** -225 -*** -255 -() -174 -*** -269 -() -173 -*** -214 -() -172 -*** -186 -() -171 -*** -447 -() -170 -*** -270 -*** -306 -() -169 -*** -336 -() -168 -*** -285 -() -165 -*** -249 -() -146 -*** -154 -() -143 -*** -334 -() -142 -*** -216 -*** -257 -() -141 -*** -167 -*** -251 -() -140 -*** -162 -*** -293 -() -139 -*** -158 -() -137 -*** -166 -*** -201 -() -136 -*** -160 -() -134 -*** -221 -() -132 -*** -213 -() -131 -*** -187 -() -129 -*** -235 -() -128 -*** -153 -() -127 -*** -156 -() -126 -*** -159 -*** -218 -() -125 -*** -155 -() -124 -*** -157 -() -123 -*** -152 -() -116 -*** -135 -*** -163 -() -115 -*** -133 -*** -204 -*** -248 -() -114 -*** -192 -*** -212 -() -113 -*** -268 -() -112 -*** -367 -() -111 -*** -272 -() -110 -*** -434 -() -109 -*** -323 -() -108 -*** -281 -() -107 -*** -144 -*** -148 -() -106 -*** -275 -() -105 -*** -196 -*** -254 -() -104 -*** -138 -*** -161 -() -103 -*** -310 -() -102 -*** -223 -*** -252 -() -80 -() -70 -() -69 -() -68 -() -66 -() -64 -() -62 -*** -256 -() -61 -*** -93 -() -59 -*** -120 -() -58 -() -57 -*** -183 -() -55 -() -54 -() -52 -*** -147 -() -51 -*** -118 -() -50 -*** -83 -() -49 -*** -98 -() -48 -*** -99 -() -47 -() -46 -*** -184 -() -45 -*** -121 -() -44 -() -43 -*** -88 -() -42 -*** -122 -() -41 -*** -91 -() -40 -*** -96 -() -38 -*** -100 -() -37 -*** -149 -() -36 -*** -74 -() -35 -*** -258 -() -34 -*** -151 -() -33 -*** -85 -() -32 -() -31 -*** -94 -() -30 -*** -97 -() -29 -*** -90 -() -28 -*** -89 -() -27 -*** -92 -() -26 -*** -72 -*** -247 -() -25 -*** -86 -() -24 -*** -82 -() -23 -*** -87 -*** -117 -() -22 -*** -76 -*** -119 -() -21 -*** -84 -() -20 -*** -78 -() -19 -*** -73 -() -18 -*** -81 -() -17 -*** -65 -() -16 -*** -63 -*** -101 -() -15 -*** -71 -() -14 -*** -75 -() -13 -*** -322 -() -12 -*** -77 -() -11 -*** -283 -() -10 -*** -79 -() -9 -*** -145 -*** -150 -() -8 -*** -67 -() -7 -*** -60 -*** -231 -() -6 -*** -56 -*** -234 -() -5 -*** -164 -*** -202 -() -4 -*** -53 -() -3 -*** -130 -*** -185 -*** -200 -() -2 -*** -205 -() -1 -*** -39 -*** -95 diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simerr b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simerr deleted file mode 100755 index 1a4f96712..000000000 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simerr +++ /dev/null @@ -1 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout deleted file mode 100755 index ea901fcca..000000000 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout +++ /dev/null @@ -1,27 +0,0 @@ -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Jan 23 2014 12:08:08 -gem5 started Jan 23 2014 17:12:31 -gem5 executing on u200540-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-timing -Global frequency set at 1000000000000 ticks per second - 0: system.cpu.isa: ISA system set to: 0 0x5565040 -info: Entering event queue @ 0. Starting simulation... - -MCF SPEC version 1.6.I -by Andreas Loebel -Copyright (c) 1998,1999 ZIB Berlin -All Rights Reserved. - -nodes : 500 -active arcs : 1905 -simplex iterations : 1502 -flow value : 4990014995 -new implicit arcs : 23867 -active arcs : 25772 -simplex iterations : 2663 -flow value : 3080014995 -checksum : 68389 -optimal -Exiting @ tick 147135976000 because target called exit() diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt deleted file mode 100644 index 7176a8af9..000000000 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt +++ /dev/null @@ -1,634 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.147041 # Number of seconds simulated -sim_ticks 147041218500 # Number of ticks simulated -final_tick 147041218500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 937429 # Simulator instruction rate (inst/s) -host_op_rate 942087 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1521808702 # Simulator tick rate (ticks/s) -host_mem_usage 442868 # Number of bytes of host memory used -host_seconds 96.62 # Real time elapsed on the host -sim_insts 90576861 # Number of instructions simulated -sim_ops 91026990 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 36992 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 944768 # Number of bytes read from this memory -system.physmem.bytes_read::total 981760 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 36992 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 36992 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 578 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 14762 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15340 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 251576 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 6425192 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6676767 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 251576 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 251576 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 251576 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 6425192 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6676767 # Total bandwidth to/from this memory (bytes/s) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 0 # Table walker walks requested -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 0 # Table walker walks requested -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 294082437 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 90576861 # Number of instructions committed -system.cpu.committedOps 91026990 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 72326352 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses -system.cpu.num_func_calls 112245 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 15520157 # number of instructions that are conditional controls -system.cpu.num_int_insts 72326352 # number of integer instructions -system.cpu.num_fp_insts 48 # number of float instructions -system.cpu.num_int_register_reads 124237033 # number of times the integer registers were read -system.cpu.num_int_register_writes 52782988 # number of times the integer registers were written -system.cpu.num_fp_register_reads 54 # number of times the floating registers were read -system.cpu.num_fp_register_writes 30 # number of times the floating registers were written -system.cpu.num_cc_register_reads 339191618 # number of times the CC registers were read -system.cpu.num_cc_register_writes 53956115 # number of times the CC registers were written -system.cpu.num_mem_refs 27220755 # number of memory refs -system.cpu.num_load_insts 22475911 # Number of load instructions -system.cpu.num_store_insts 4744844 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 294082436.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 18732304 # Number of branches fetched -system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 63822828 70.09% 70.09% # Class of executed instruction -system.cpu.op_class::IntMult 10474 0.01% 70.10% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 6 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 15 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 2 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::MemRead 22475911 24.68% 94.79% # Class of executed instruction -system.cpu.op_class::MemWrite 4744844 5.21% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 91054080 # Class of executed instruction -system.cpu.dcache.tags.replacements 942702 # number of replacements -system.cpu.dcache.tags.tagsinuse 3565.593939 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 26253601 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 946798 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 27.728830 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 54410414000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3565.593939 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.870506 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.870506 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 135 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1355 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2550 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 56 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 55347598 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 55347598 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 21556948 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21556948 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4688372 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4688372 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 507 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 507 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 26245320 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26245320 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 26245827 # number of overall hits -system.cpu.dcache.overall_hits::total 26245827 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 900187 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 900187 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 46609 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 46609 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 3 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 3 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 946796 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 946796 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 946799 # number of overall misses -system.cpu.dcache.overall_misses::total 946799 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11711364000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11711364000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1217183500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1217183500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 12928547500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 12928547500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 12928547500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 12928547500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22457135 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22457135 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 510 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 510 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 27192116 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 27192116 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 27192626 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 27192626 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040085 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.040085 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009844 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.009844 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.005882 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.005882 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.034819 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.034819 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.034818 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.034818 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13009.923494 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13009.923494 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26114.773971 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 26114.773971 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 13655.050824 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 13655.050824 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 13655.007557 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 13655.007557 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 942334 # number of writebacks -system.cpu.dcache.writebacks::total 942334 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 900186 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 900186 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46609 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 46609 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 946795 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 946795 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 946798 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 946798 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10361045000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10361045000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1147270000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1147270000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 118500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 118500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11508315000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11508315000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11508433500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11508433500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040085 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040085 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009844 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009844 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.005882 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.005882 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034819 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.034819 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034818 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.034818 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11509.893511 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11509.893511 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24614.773971 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24614.773971 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 39500 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 39500 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12155.022999 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 12155.022999 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12155.109643 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 12155.109643 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 2 # number of replacements -system.cpu.icache.tags.tagsinuse 510.120572 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 107830172 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 599 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 180016.981636 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.120572 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.249082 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.249082 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 597 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 552 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.291504 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 215662141 # Number of tag accesses -system.cpu.icache.tags.data_accesses 215662141 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 107830172 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 107830172 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 107830172 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 107830172 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 107830172 # number of overall hits -system.cpu.icache.overall_hits::total 107830172 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 599 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 599 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 599 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 599 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 599 # number of overall misses -system.cpu.icache.overall_misses::total 599 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 32074000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 32074000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 32074000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 32074000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 32074000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 32074000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 107830771 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 107830771 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 107830771 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 107830771 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 107830771 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 107830771 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000006 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000006 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000006 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000006 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000006 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000006 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53545.909850 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 53545.909850 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 53545.909850 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 53545.909850 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 53545.909850 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 53545.909850 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 599 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 599 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 599 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 599 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 599 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 599 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 31175500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 31175500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 31175500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 31175500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 31175500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 31175500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000006 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000006 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000006 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52045.909850 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52045.909850 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52045.909850 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 52045.909850 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52045.909850 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 52045.909850 # average overall mshr miss latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 9567.852421 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1827177 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 15323 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 119.244078 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 8879.446344 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 495.172977 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 193.233100 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.270979 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.015111 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.005897 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.291988 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 15323 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 105 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1468 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13704 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.467621 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 15179780 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 15179780 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 21 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 899975 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 899996 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 942334 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 942334 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 32061 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 32061 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 21 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 932036 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 932057 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 21 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 932036 # number of overall hits -system.cpu.l2cache.overall_hits::total 932057 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 578 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 214 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 792 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 14548 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 14548 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 578 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 14762 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 15340 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 578 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 14762 # number of overall misses -system.cpu.l2cache.overall_misses::total 15340 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 30356000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11237000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 41593000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 764020500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 764020500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 30356000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 775257500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 805613500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 30356000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 775257500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 805613500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 599 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 900189 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 900788 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 942334 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 942334 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 46609 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 46609 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 599 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 946798 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 947397 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 599 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 946798 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 947397 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.964942 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000238 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.000879 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.312129 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.312129 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.964942 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.015591 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.016192 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.964942 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.015591 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.016192 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52519.031142 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52509.345794 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52516.414141 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52517.218862 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52517.218862 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52519.031142 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52517.104728 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52517.177314 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52519.031142 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52517.104728 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52517.177314 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 578 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 214 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 792 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14548 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 14548 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 578 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 14762 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 15340 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 578 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 14762 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 15340 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 23409000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8667000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 32076000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 589194000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 589194000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23409000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 597861000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 621270000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23409000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 597861000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 621270000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.964942 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000238 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000879 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.312129 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.312129 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.964942 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015591 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.016192 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.964942 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015591 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.016192 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 900788 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 900788 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 942334 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 46609 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 46609 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1198 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2835930 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2837128 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 38336 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120904448 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 120942784 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 1889731 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 1889731 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1889731 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 1887199500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 898500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1420197000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) -system.membus.trans_dist::ReadReq 792 # Transaction distribution -system.membus.trans_dist::ReadResp 792 # Transaction distribution -system.membus.trans_dist::ReadExReq 14548 # Transaction distribution -system.membus.trans_dist::ReadExResp 14548 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 30680 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 30680 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 981760 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 981760 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 15340 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 15340 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 15340 # Request fanout histogram -system.membus.reqLayer0.occupancy 15603500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 76963500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.1 # Layer utilization (%) - ----------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini deleted file mode 100644 index 5a8877655..000000000 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini +++ /dev/null @@ -1,171 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -eventq_index=0 -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=atomic -mem_ranges= -memories=system.physmem -num_work_ids=16 -readfile= -symbolfile= -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=AtomicSimpleCPU -children=dtb interrupts isa itb tracer workload -branchPred=Null -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -eventq_index=0 -fastmem=false -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -profile=0 -progress_interval=0 -simpoint_start_insts= -simulate_data_stalls=false -simulate_inst_stalls=false -socket_id=0 -switched_out=false -system=system -tracer=system.cpu.tracer -width=1 -workload=system.cpu.workload -dcache_port=system.membus.slave[2] -icache_port=system.membus.slave[1] - -[system.cpu.dtb] -type=SparcTLB -eventq_index=0 -size=64 - -[system.cpu.interrupts] -type=SparcInterrupts -eventq_index=0 - -[system.cpu.isa] -type=SparcISA -eventq_index=0 - -[system.cpu.itb] -type=SparcTLB -eventq_index=0 -size=64 - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=mcf mcf.in -cwd=build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-atomic -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/sparc/linux/mcf -gid=100 -input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=55300000000 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -clk_domain=system.clk_domain -eventq_index=0 -header_cycles=1 -snoop_filter=Null -system=system -use_default_range=false -width=8 -master=system.physmem.port -slave=system.system_port system.cpu.icache_port system.cpu.dcache_port - -[system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=true -eventq_index=0 -in_addr_map=true -latency=30000 -latency_var=0 -null=false -range=0:268435455 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/mcf.out b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/mcf.out deleted file mode 100644 index 095132477..000000000 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/mcf.out +++ /dev/null @@ -1,999 +0,0 @@ -() -500 -() -499 -() -498 -() -496 -() -495 -() -494 -() -493 -() -492 -() -491 -() -490 -() -489 -() -488 -() -487 -() -486 -() -484 -() -482 -() -481 -() -480 -() -479 -() -478 -() -477 -() -476 -() -475 -() -474 -() -473 -() -472 -() -471 -() -469 -() -468 -() -467 -() -466 -() -465 -() -464 -() -463 -() -462 -() -461 -() -460 -() -459 -() -458 -() -457 -() -455 -() -454 -() -452 -() -451 -() -450 -() -449 -() -448 -() -446 -() -445 -() -444 -() -443 -() -442 -() -440 -() -439 -() -438 -() -436 -() -435 -() -433 -() -432 -() -431 -() -428 -() -427 -() -425 -() -424 -() -423 -() -420 -() -419 -() -416 -() -414 -() -413 -() -412 -() -407 -() -406 -() -405 -() -404 -() -403 -() -402 -() -401 -() -400 -() -399 -() -398 -() -396 -() -395 -() -393 -() -392 -() -390 -() -389 -() -388 -() -387 -() -386 -() -385 -() -384 -() -383 -() -382 -() -381 -() -380 -() -379 -() -377 -() -375 -() -374 -() -373 -() -372 -() -371 -() -370 -() -369 -() -368 -() -366 -() -365 -() -364 -() -362 -() -361 -() -360 -() -359 -() -358 -() -357 -() -356 -() -355 -() -354 -() -352 -() -350 -() -347 -() -344 -() -342 -() -341 -() -340 -() -339 -() -338 -() -332 -() -325 -() -320 -*** -345 -() -319 -*** -497 -() -318 -*** -349 -() -317 -*** -408 -() -316 -*** -324 -() -315 -*** -328 -() -314 -*** -335 -() -313 -*** -378 -() -312 -*** -426 -() -311 -*** -411 -() -304 -*** -343 -() -303 -*** -417 -() -302 -*** -485 -() -301 -*** -363 -() -300 -*** -376 -() -299 -*** -333 -() -292 -*** -337 -() -291 -*** -409 -() -290 -*** -421 -() -289 -*** -437 -() -288 -*** -430 -() -287 -*** -348 -() -286 -*** -326 -() -284 -() -282 -*** -308 -() -279 -*** -297 -*** -305 -() -278 -() -277 -*** -307 -() -276 -*** -296 -() -273 -() -271 -() -265 -() -246 -*** -267 -() -245 -*** -280 -() -244 -*** -391 -() -243 -*** -330 -() -242 -*** -456 -() -241 -*** -346 -() -240 -*** -483 -() -239 -*** -260 -() -238 -*** -261 -() -237 -*** -262 -*** -294 -() -236 -*** -253 -() -229 -*** -397 -() -228 -*** -298 -() -227 -*** -415 -() -226 -*** -264 -() -224 -*** -232 -() -222 -*** -233 -() -217 -*** -250 -() -211 -*** -331 -() -210 -*** -394 -() -209 -*** -410 -() -208 -*** -321 -() -207 -*** -327 -() -206 -*** -309 -() -199 -*** -259 -() -198 -*** -219 -() -197 -*** -220 -() -195 -*** -429 -() -194 -*** -470 -() -193 -*** -274 -() -191 -*** -203 -() -190 -*** -263 -() -189 -215 -*** -230 -() -188 -*** -266 -*** -295 -() -182 -*** -329 -() -181 -*** -351 -() -180 -*** -441 -() -179 -*** -453 -() -178 -*** -418 -() -177 -*** -353 -() -176 -*** -422 -() -175 -*** -225 -*** -255 -() -174 -*** -269 -() -173 -*** -214 -() -172 -*** -186 -() -171 -*** -447 -() -170 -*** -270 -*** -306 -() -169 -*** -336 -() -168 -*** -285 -() -165 -*** -249 -() -146 -*** -154 -() -143 -*** -334 -() -142 -*** -216 -*** -257 -() -141 -*** -167 -*** -251 -() -140 -*** -162 -*** -293 -() -139 -*** -158 -() -137 -*** -166 -*** -201 -() -136 -*** -160 -() -134 -*** -221 -() -132 -*** -213 -() -131 -*** -187 -() -129 -*** -235 -() -128 -*** -153 -() -127 -*** -156 -() -126 -*** -159 -*** -218 -() -125 -*** -155 -() -124 -*** -157 -() -123 -*** -152 -() -116 -*** -135 -*** -163 -() -115 -*** -133 -*** -204 -*** -248 -() -114 -*** -192 -*** -212 -() -113 -*** -268 -() -112 -*** -367 -() -111 -*** -272 -() -110 -*** -434 -() -109 -*** -323 -() -108 -*** -281 -() -107 -*** -144 -*** -148 -() -106 -*** -275 -() -105 -*** -196 -*** -254 -() -104 -*** -138 -*** -161 -() -103 -*** -310 -() -102 -*** -223 -*** -252 -() -80 -() -70 -() -69 -() -68 -() -66 -() -64 -() -62 -*** -256 -() -61 -*** -93 -() -59 -*** -120 -() -58 -() -57 -*** -183 -() -55 -() -54 -() -52 -*** -147 -() -51 -*** -118 -() -50 -*** -83 -() -49 -*** -98 -() -48 -*** -99 -() -47 -() -46 -*** -184 -() -45 -*** -121 -() -44 -() -43 -*** -88 -() -42 -*** -122 -() -41 -*** -91 -() -40 -*** -96 -() -38 -*** -100 -() -37 -*** -149 -() -36 -*** -74 -() -35 -*** -258 -() -34 -*** -151 -() -33 -*** -85 -() -32 -() -31 -*** -94 -() -30 -*** -97 -() -29 -*** -90 -() -28 -*** -89 -() -27 -*** -92 -() -26 -*** -72 -*** -247 -() -25 -*** -86 -() -24 -*** -82 -() -23 -*** -87 -*** -117 -() -22 -*** -76 -*** -119 -() -21 -*** -84 -() -20 -*** -78 -() -19 -*** -73 -() -18 -*** -81 -() -17 -*** -65 -() -16 -*** -63 -*** -101 -() -15 -*** -71 -() -14 -*** -75 -() -13 -*** -322 -() -12 -*** -77 -() -11 -*** -283 -() -10 -*** -79 -() -9 -*** -145 -*** -150 -() -8 -*** -67 -() -7 -*** -60 -*** -231 -() -6 -*** -56 -*** -234 -() -5 -*** -164 -*** -202 -() -4 -*** -53 -() -3 -*** -130 -*** -185 -*** -200 -() -2 -*** -205 -() -1 -*** -39 -*** -95 diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simerr b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simerr deleted file mode 100755 index 1a4f96712..000000000 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simerr +++ /dev/null @@ -1 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout deleted file mode 100755 index a8897be0c..000000000 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout +++ /dev/null @@ -1,26 +0,0 @@ -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Jan 22 2014 17:04:27 -gem5 started Jan 22 2014 19:41:52 -gem5 executing on u200540-lin -command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-atomic -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... - -MCF SPEC version 1.6.I -by Andreas Loebel -Copyright (c) 1998,1999 ZIB Berlin -All Rights Reserved. - -nodes : 500 -active arcs : 1905 -simplex iterations : 1502 -flow value : 4990014995 -new implicit arcs : 23867 -active arcs : 25772 -simplex iterations : 2663 -flow value : 3080014995 -checksum : 68389 -optimal -Exiting @ tick 122215823500 because target called exit() diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt deleted file mode 100644 index c1c851704..000000000 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt +++ /dev/null @@ -1,124 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.122216 # Number of seconds simulated -sim_ticks 122215823500 # Number of ticks simulated -final_tick 122215823500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2069444 # Simulator instruction rate (inst/s) -host_op_rate 2069529 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1037295392 # Simulator tick rate (ticks/s) -host_mem_usage 412436 # Number of bytes of host memory used -host_seconds 117.82 # Real time elapsed on the host -sim_insts 243825150 # Number of instructions simulated -sim_ops 243835265 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 977685992 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 328674008 # Number of bytes read from this memory -system.physmem.bytes_read::total 1306360000 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 977685992 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 977685992 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 91606089 # Number of bytes written to this memory -system.physmem.bytes_written::total 91606089 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 244421498 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 82220433 # Number of read requests responded to by this memory -system.physmem.num_reads::total 326641931 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 22901951 # Number of write requests responded to by this memory -system.physmem.num_writes::total 22901951 # Number of write requests responded to by this memory -system.physmem.num_other::cpu.data 3886 # Number of other requests responded to by this memory -system.physmem.num_other::total 3886 # Number of other requests responded to by this memory -system.physmem.bw_read::cpu.inst 7999667834 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2689291768 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 10688959601 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7999667834 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7999667834 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 749543606 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 749543606 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7999667834 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3438835373 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 11438503207 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 326641931 # Transaction distribution -system.membus.trans_dist::ReadResp 326641931 # Transaction distribution -system.membus.trans_dist::WriteReq 22901951 # Transaction distribution -system.membus.trans_dist::WriteResp 22901951 # Transaction distribution -system.membus.trans_dist::SwapReq 3886 # Transaction distribution -system.membus.trans_dist::SwapResp 3886 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 488842996 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 210252540 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 699095536 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 977685992 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 420311185 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1397997177 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 349547768 # Request fanout histogram -system.membus.snoop_fanout::mean 0.699251 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.458584 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 105126270 30.07% 30.07% # Request fanout histogram -system.membus.snoop_fanout::1 244421498 69.93% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 349547768 # Request fanout histogram -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.workload.num_syscalls 443 # Number of system calls -system.cpu.numCycles 244431648 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 243825150 # Number of instructions committed -system.cpu.committedOps 243835265 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 194726494 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 11630 # Number of float alu accesses -system.cpu.num_func_calls 4252956 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 18619959 # number of instructions that are conditional controls -system.cpu.num_int_insts 194726494 # number of integer instructions -system.cpu.num_fp_insts 11630 # number of float instructions -system.cpu.num_int_register_reads 456818988 # number of times the integer registers were read -system.cpu.num_int_register_writes 215451554 # number of times the integer registers were written -system.cpu.num_fp_register_reads 23256 # number of times the floating registers were read -system.cpu.num_fp_register_writes 90 # number of times the floating registers were written -system.cpu.num_mem_refs 105711441 # number of memory refs -system.cpu.num_load_insts 82803521 # Number of load instructions -system.cpu.num_store_insts 22907920 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 244431647.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 29302884 # Number of branches fetched -system.cpu.op_class::No_OpClass 28877736 11.81% 11.81% # Class of executed instruction -system.cpu.op_class::IntAlu 109842388 44.94% 56.75% # Class of executed instruction -system.cpu.op_class::IntMult 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::FloatAdd 42 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::MemRead 82803527 33.88% 90.63% # Class of executed instruction -system.cpu.op_class::MemWrite 22907920 9.37% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 244431613 # Class of executed instruction - ----------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini deleted file mode 100644 index 519142696..000000000 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini +++ /dev/null @@ -1,207 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -eventq_index=0 -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=atomic -mem_ranges= -memories=system.physmem -num_work_ids=16 -readfile= -symbolfile= -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=AtomicSimpleCPU -children=apic_clk_domain dtb interrupts isa itb tracer workload -branchPred=Null -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -eventq_index=0 -fastmem=false -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -profile=0 -progress_interval=0 -simpoint_start_insts= -simulate_data_stalls=false -simulate_inst_stalls=false -socket_id=0 -switched_out=false -system=system -tracer=system.cpu.tracer -width=1 -workload=system.cpu.workload -dcache_port=system.membus.slave[2] -icache_port=system.membus.slave[1] - -[system.cpu.apic_clk_domain] -type=DerivedClockDomain -clk_divider=16 -clk_domain=system.cpu_clk_domain -eventq_index=0 - -[system.cpu.dtb] -type=X86TLB -children=walker -eventq_index=0 -size=64 -walker=system.cpu.dtb.walker - -[system.cpu.dtb.walker] -type=X86PagetableWalker -clk_domain=system.cpu_clk_domain -eventq_index=0 -num_squash_per_cycle=4 -system=system -port=system.membus.slave[4] - -[system.cpu.interrupts] -type=X86LocalApic -clk_domain=system.cpu.apic_clk_domain -eventq_index=0 -int_latency=1000 -pio_addr=2305843009213693952 -pio_latency=100000 -system=system -int_master=system.membus.slave[5] -int_slave=system.membus.master[2] -pio=system.membus.master[1] - -[system.cpu.isa] -type=X86ISA -eventq_index=0 - -[system.cpu.itb] -type=X86TLB -children=walker -eventq_index=0 -size=64 -walker=system.cpu.itb.walker - -[system.cpu.itb.walker] -type=X86PagetableWalker -clk_domain=system.cpu_clk_domain -eventq_index=0 -num_squash_per_cycle=4 -system=system -port=system.membus.slave[3] - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=mcf mcf.in -cwd=build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/mcf -gid=100 -input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=55300000000 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -clk_domain=system.clk_domain -eventq_index=0 -header_cycles=1 -snoop_filter=Null -system=system -use_default_range=false -width=8 -master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave -slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.int_master - -[system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=true -eventq_index=0 -in_addr_map=true -latency=30000 -latency_var=0 -null=false -range=0:268435455 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/mcf.out b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/mcf.out deleted file mode 100644 index 095132477..000000000 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/mcf.out +++ /dev/null @@ -1,999 +0,0 @@ -() -500 -() -499 -() -498 -() -496 -() -495 -() -494 -() -493 -() -492 -() -491 -() -490 -() -489 -() -488 -() -487 -() -486 -() -484 -() -482 -() -481 -() -480 -() -479 -() -478 -() -477 -() -476 -() -475 -() -474 -() -473 -() -472 -() -471 -() -469 -() -468 -() -467 -() -466 -() -465 -() -464 -() -463 -() -462 -() -461 -() -460 -() -459 -() -458 -() -457 -() -455 -() -454 -() -452 -() -451 -() -450 -() -449 -() -448 -() -446 -() -445 -() -444 -() -443 -() -442 -() -440 -() -439 -() -438 -() -436 -() -435 -() -433 -() -432 -() -431 -() -428 -() -427 -() -425 -() -424 -() -423 -() -420 -() -419 -() -416 -() -414 -() -413 -() -412 -() -407 -() -406 -() -405 -() -404 -() -403 -() -402 -() -401 -() -400 -() -399 -() -398 -() -396 -() -395 -() -393 -() -392 -() -390 -() -389 -() -388 -() -387 -() -386 -() -385 -() -384 -() -383 -() -382 -() -381 -() -380 -() -379 -() -377 -() -375 -() -374 -() -373 -() -372 -() -371 -() -370 -() -369 -() -368 -() -366 -() -365 -() -364 -() -362 -() -361 -() -360 -() -359 -() -358 -() -357 -() -356 -() -355 -() -354 -() -352 -() -350 -() -347 -() -344 -() -342 -() -341 -() -340 -() -339 -() -338 -() -332 -() -325 -() -320 -*** -345 -() -319 -*** -497 -() -318 -*** -349 -() -317 -*** -408 -() -316 -*** -324 -() -315 -*** -328 -() -314 -*** -335 -() -313 -*** -378 -() -312 -*** -426 -() -311 -*** -411 -() -304 -*** -343 -() -303 -*** -417 -() -302 -*** -485 -() -301 -*** -363 -() -300 -*** -376 -() -299 -*** -333 -() -292 -*** -337 -() -291 -*** -409 -() -290 -*** -421 -() -289 -*** -437 -() -288 -*** -430 -() -287 -*** -348 -() -286 -*** -326 -() -284 -() -282 -*** -308 -() -279 -*** -297 -*** -305 -() -278 -() -277 -*** -307 -() -276 -*** -296 -() -273 -() -271 -() -265 -() -246 -*** -267 -() -245 -*** -280 -() -244 -*** -391 -() -243 -*** -330 -() -242 -*** -456 -() -241 -*** -346 -() -240 -*** -483 -() -239 -*** -260 -() -238 -*** -261 -() -237 -*** -262 -*** -294 -() -236 -*** -253 -() -229 -*** -397 -() -228 -*** -298 -() -227 -*** -415 -() -226 -*** -264 -() -224 -*** -232 -() -222 -*** -233 -() -217 -*** -250 -() -211 -*** -331 -() -210 -*** -394 -() -209 -*** -410 -() -208 -*** -321 -() -207 -*** -327 -() -206 -*** -309 -() -199 -*** -259 -() -198 -*** -219 -() -197 -*** -220 -() -195 -*** -429 -() -194 -*** -470 -() -193 -*** -274 -() -191 -*** -203 -() -190 -*** -263 -() -189 -215 -*** -230 -() -188 -*** -266 -*** -295 -() -182 -*** -329 -() -181 -*** -351 -() -180 -*** -441 -() -179 -*** -453 -() -178 -*** -418 -() -177 -*** -353 -() -176 -*** -422 -() -175 -*** -225 -*** -255 -() -174 -*** -269 -() -173 -*** -214 -() -172 -*** -186 -() -171 -*** -447 -() -170 -*** -270 -*** -306 -() -169 -*** -336 -() -168 -*** -285 -() -165 -*** -249 -() -146 -*** -154 -() -143 -*** -334 -() -142 -*** -216 -*** -257 -() -141 -*** -167 -*** -251 -() -140 -*** -162 -*** -293 -() -139 -*** -158 -() -137 -*** -166 -*** -201 -() -136 -*** -160 -() -134 -*** -221 -() -132 -*** -213 -() -131 -*** -187 -() -129 -*** -235 -() -128 -*** -153 -() -127 -*** -156 -() -126 -*** -159 -*** -218 -() -125 -*** -155 -() -124 -*** -157 -() -123 -*** -152 -() -116 -*** -135 -*** -163 -() -115 -*** -133 -*** -204 -*** -248 -() -114 -*** -192 -*** -212 -() -113 -*** -268 -() -112 -*** -367 -() -111 -*** -272 -() -110 -*** -434 -() -109 -*** -323 -() -108 -*** -281 -() -107 -*** -144 -*** -148 -() -106 -*** -275 -() -105 -*** -196 -*** -254 -() -104 -*** -138 -*** -161 -() -103 -*** -310 -() -102 -*** -223 -*** -252 -() -80 -() -70 -() -69 -() -68 -() -66 -() -64 -() -62 -*** -256 -() -61 -*** -93 -() -59 -*** -120 -() -58 -() -57 -*** -183 -() -55 -() -54 -() -52 -*** -147 -() -51 -*** -118 -() -50 -*** -83 -() -49 -*** -98 -() -48 -*** -99 -() -47 -() -46 -*** -184 -() -45 -*** -121 -() -44 -() -43 -*** -88 -() -42 -*** -122 -() -41 -*** -91 -() -40 -*** -96 -() -38 -*** -100 -() -37 -*** -149 -() -36 -*** -74 -() -35 -*** -258 -() -34 -*** -151 -() -33 -*** -85 -() -32 -() -31 -*** -94 -() -30 -*** -97 -() -29 -*** -90 -() -28 -*** -89 -() -27 -*** -92 -() -26 -*** -72 -*** -247 -() -25 -*** -86 -() -24 -*** -82 -() -23 -*** -87 -*** -117 -() -22 -*** -76 -*** -119 -() -21 -*** -84 -() -20 -*** -78 -() -19 -*** -73 -() -18 -*** -81 -() -17 -*** -65 -() -16 -*** -63 -*** -101 -() -15 -*** -71 -() -14 -*** -75 -() -13 -*** -322 -() -12 -*** -77 -() -11 -*** -283 -() -10 -*** -79 -() -9 -*** -145 -*** -150 -() -8 -*** -67 -() -7 -*** -60 -*** -231 -() -6 -*** -56 -*** -234 -() -5 -*** -164 -*** -202 -() -4 -*** -53 -() -3 -*** -130 -*** -185 -*** -200 -() -2 -*** -205 -() -1 -*** -39 -*** -95 diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simerr b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simerr deleted file mode 100755 index 1a4f96712..000000000 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simerr +++ /dev/null @@ -1 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout deleted file mode 100755 index ea41249d4..000000000 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout +++ /dev/null @@ -1,26 +0,0 @@ -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Jan 22 2014 17:10:34 -gem5 started Jan 22 2014 20:16:46 -gem5 executing on u200540-lin -command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... - -MCF SPEC version 1.6.I -by Andreas Loebel -Copyright (c) 1998,1999 ZIB Berlin -All Rights Reserved. - -nodes : 500 -active arcs : 1905 -simplex iterations : 1502 -flow value : 4990014995 -new implicit arcs : 23867 -active arcs : 25772 -simplex iterations : 2663 -flow value : 3080014995 -checksum : 68389 -optimal -Exiting @ tick 168950040000 because target called exit() diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt deleted file mode 100644 index 844bb352a..000000000 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt +++ /dev/null @@ -1,129 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.168950 # Number of seconds simulated -sim_ticks 168950040000 # Number of ticks simulated -final_tick 168950040000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1180838 # Simulator instruction rate (inst/s) -host_op_rate 2079266 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1262766288 # Simulator tick rate (ticks/s) -host_mem_usage 436624 # Number of bytes of host memory used -host_seconds 133.79 # Real time elapsed on the host -sim_insts 157988548 # Number of instructions simulated -sim_ops 278192465 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 1741569312 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 717246013 # Number of bytes read from this memory -system.physmem.bytes_read::total 2458815325 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1741569312 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1741569312 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 243173117 # Number of bytes written to this memory -system.physmem.bytes_written::total 243173117 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 217696164 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 90779447 # Number of read requests responded to by this memory -system.physmem.num_reads::total 308475611 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 31439752 # Number of write requests responded to by this memory -system.physmem.num_writes::total 31439752 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 10308191179 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 4245314254 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14553505433 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 10308191179 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 10308191179 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1439319677 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1439319677 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 10308191179 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5684633931 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 15992825110 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 308475611 # Transaction distribution -system.membus.trans_dist::ReadResp 308475611 # Transaction distribution -system.membus.trans_dist::WriteReq 31439752 # Transaction distribution -system.membus.trans_dist::WriteResp 31439752 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 435392328 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.icache_port::total 435392328 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 244438398 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::total 244438398 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 679830726 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1741569312 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::total 1741569312 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 960419130 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::total 960419130 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 2701988442 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 339915363 # Request fanout histogram -system.membus.snoop_fanout::mean 2.640442 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.479871 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::2 122219199 35.96% 35.96% # Request fanout histogram -system.membus.snoop_fanout::3 217696164 64.04% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 2 # Request fanout histogram -system.membus.snoop_fanout::max_value 3 # Request fanout histogram -system.membus.snoop_fanout::total 339915363 # Request fanout histogram -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.workload.num_syscalls 444 # Number of system calls -system.cpu.numCycles 337900081 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 157988548 # Number of instructions committed -system.cpu.committedOps 278192465 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 278169482 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses -system.cpu.num_func_calls 8475189 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 18628007 # number of instructions that are conditional controls -system.cpu.num_int_insts 278169482 # number of integer instructions -system.cpu.num_fp_insts 40 # number of float instructions -system.cpu.num_int_register_reads 635379407 # number of times the integer registers were read -system.cpu.num_int_register_writes 217447860 # number of times the integer registers were written -system.cpu.num_fp_register_reads 40 # number of times the floating registers were read -system.cpu.num_fp_register_writes 26 # number of times the floating registers were written -system.cpu.num_cc_register_reads 104140596 # number of times the CC registers were read -system.cpu.num_cc_register_writes 61764861 # number of times the CC registers were written -system.cpu.num_mem_refs 122219137 # number of memory refs -system.cpu.num_load_insts 90779385 # Number of load instructions -system.cpu.num_store_insts 31439752 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 337900080.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 29309705 # Number of branches fetched -system.cpu.op_class::No_OpClass 16695 0.01% 0.01% # Class of executed instruction -system.cpu.op_class::IntAlu 155945354 56.06% 56.06% # Class of executed instruction -system.cpu.op_class::IntMult 10938 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::IntDiv 329 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::FloatAdd 12 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::MemRead 90779385 32.63% 88.70% # Class of executed instruction -system.cpu.op_class::MemWrite 31439752 11.30% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 278192465 # Class of executed instruction - ----------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini deleted file mode 100644 index 44bc5cf02..000000000 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini +++ /dev/null @@ -1,172 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -eventq_index=0 -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=atomic -mem_ranges= -memories=system.physmem -num_work_ids=16 -readfile= -symbolfile= -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=AtomicSimpleCPU -children=dtb interrupts isa itb tracer workload -branchPred=Null -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -eventq_index=0 -fastmem=false -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -profile=0 -progress_interval=0 -simpoint_start_insts= -simulate_data_stalls=false -simulate_inst_stalls=false -socket_id=0 -switched_out=false -system=system -tracer=system.cpu.tracer -width=1 -workload=system.cpu.workload -dcache_port=system.membus.slave[2] -icache_port=system.membus.slave[1] - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook -cwd=build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-atomic -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/eon -gid=100 -input=cin -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -clk_domain=system.clk_domain -eventq_index=0 -header_cycles=1 -snoop_filter=Null -system=system -use_default_range=false -width=8 -master=system.physmem.port -slave=system.system_port system.cpu.icache_port system.cpu.dcache_port - -[system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=true -eventq_index=0 -in_addr_map=true -latency=30000 -latency_var=0 -null=false -range=0:134217727 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simerr b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simerr deleted file mode 100755 index 664365742..000000000 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simerr +++ /dev/null @@ -1,51 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -getting pixel output filename pixels_out.cook -opening control file chair.control.cook -opening camera file chair.camera -opening surfaces file chair.surfaces -reading data -processing 8parts -Grid measure is 6 by 3.0001 by 6 -cell dimension is 0.863065 -Creating grid for list of length 21 -Grid size = 7 by 4 by 7 -Total occupancy = 236 -reading control stream -reading camera stream -Writing to chair.cook.ppm -calculating 15 by 15 image with 196 samples -col 0. . . -col 1. . . -col 2. . . -col 3. . . -col 4. . . -col 5. . . -col 6. . . -col 7. . . -col 8. . . -col 9. . . -col 10. . . -col 11. . . -col 12. . . -col 13. . . -col 14. . . -Writing to chair.cook.ppm -0 8 14 -1 8 14 -2 8 14 -3 8 14 -4 8 14 -5 8 14 -6 8 14 -7 8 14 -8 8 14 -9 8 14 -10 8 14 -11 8 14 -12 8 14 -13 8 14 -14 8 14 -warn: ignoring syscall sigprocmask(1, ...) diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simout b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simout deleted file mode 100755 index e4df23735..000000000 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simout +++ /dev/null @@ -1,14 +0,0 @@ -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Jan 22 2014 16:27:55 -gem5 started Jan 22 2014 17:48:27 -gem5 executing on u200540-lin -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-atomic -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -Eon, Version 1.1 -info: Increasing stack size by one page. -OO-style eon Time= 0.183333 -Exiting @ tick 199332411500 because target called exit() diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt deleted file mode 100644 index 7803b8dd6..000000000 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt +++ /dev/null @@ -1,152 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.199332 # Number of seconds simulated -sim_ticks 199332411500 # Number of ticks simulated -final_tick 199332411500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2820224 # Simulator instruction rate (inst/s) -host_op_rate 2820224 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1410112599 # Simulator tick rate (ticks/s) -host_mem_usage 285836 # Number of bytes of host memory used -host_seconds 141.36 # Real time elapsed on the host -sim_insts 398664595 # Number of instructions simulated -sim_ops 398664595 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 1594658604 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 662449271 # Number of bytes read from this memory -system.physmem.bytes_read::total 2257107875 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1594658604 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1594658604 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 492356798 # Number of bytes written to this memory -system.physmem.bytes_written::total 492356798 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 398664651 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 94754489 # Number of read requests responded to by this memory -system.physmem.num_reads::total 493419140 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 73520729 # Number of write requests responded to by this memory -system.physmem.num_writes::total 73520729 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7999996548 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3323339471 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 11323336020 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7999996548 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7999996548 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 2470028804 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2470028804 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7999996548 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5793368275 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 13793364824 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 493419140 # Transaction distribution -system.membus.trans_dist::ReadResp 493419140 # Transaction distribution -system.membus.trans_dist::WriteReq 73520729 # Transaction distribution -system.membus.trans_dist::WriteResp 73520729 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 797329302 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 336550436 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1133879738 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1594658604 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 1154806069 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 2749464673 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 566939869 # Request fanout histogram -system.membus.snoop_fanout::mean 0.703187 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.456853 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 168275218 29.68% 29.68% # Request fanout histogram -system.membus.snoop_fanout::1 398664651 70.32% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 566939869 # Request fanout histogram -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 94754489 # DTB read hits -system.cpu.dtb.read_misses 21 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 94754510 # DTB read accesses -system.cpu.dtb.write_hits 73520729 # DTB write hits -system.cpu.dtb.write_misses 35 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 73520764 # DTB write accesses -system.cpu.dtb.data_hits 168275218 # DTB hits -system.cpu.dtb.data_misses 56 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 168275274 # DTB accesses -system.cpu.itb.fetch_hits 398664651 # ITB hits -system.cpu.itb.fetch_misses 173 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 398664824 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 398664824 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 398664595 # Number of instructions committed -system.cpu.committedOps 398664595 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 316365907 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 155295119 # Number of float alu accesses -system.cpu.num_func_calls 16015498 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 25997787 # number of instructions that are conditional controls -system.cpu.num_int_insts 316365907 # number of integer instructions -system.cpu.num_fp_insts 155295119 # number of float instructions -system.cpu.num_int_register_reads 372938760 # number of times the integer registers were read -system.cpu.num_int_register_writes 159335860 # number of times the integer registers were written -system.cpu.num_fp_register_reads 151776196 # number of times the floating registers were read -system.cpu.num_fp_register_writes 100196481 # number of times the floating registers were written -system.cpu.num_mem_refs 168275274 # number of memory refs -system.cpu.num_load_insts 94754510 # Number of load instructions -system.cpu.num_store_insts 73520764 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 398664824 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 44587532 # Number of branches fetched -system.cpu.op_class::No_OpClass 23123356 5.80% 5.80% # Class of executed instruction -system.cpu.op_class::IntAlu 141652555 35.53% 41.33% # Class of executed instruction -system.cpu.op_class::IntMult 2124322 0.53% 41.86% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 41.86% # Class of executed instruction -system.cpu.op_class::FloatAdd 35620060 8.93% 50.80% # Class of executed instruction -system.cpu.op_class::FloatCmp 7072549 1.77% 52.57% # Class of executed instruction -system.cpu.op_class::FloatCvt 2735231 0.69% 53.26% # Class of executed instruction -system.cpu.op_class::FloatMult 16498021 4.14% 57.40% # Class of executed instruction -system.cpu.op_class::FloatDiv 1563283 0.39% 57.79% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::MemRead 94754510 23.77% 81.56% # Class of executed instruction -system.cpu.op_class::MemWrite 73520764 18.44% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 398664651 # Class of executed instruction - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini new file mode 100644 index 000000000..8c1381ed5 --- /dev/null +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini @@ -0,0 +1,1361 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=true +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=LinuxArmSystem +children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain +atags_addr=134217728 +boot_loader=/dist/binaries/boot_emm.arm +boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 +boot_release_addr=65528 +cache_line_size=64 +clk_domain=system.clk_domain +dtb_filename=/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb +early_kernel_symbols=false +enable_context_switch_stats_dump=false +eventq_index=0 +flags_addr=469827632 +gic_cpu_addr=738205696 +have_generic_timer=false +have_large_asid_64=false +have_lpae=false +have_security=false +have_virtualization=false +highest_el_is_64=false +init_param=0 +kernel=/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 +kernel_addr_check=true +load_addr_mask=268435455 +load_offset=2147483648 +machine_type=VExpress_EMM +mem_mode=timing +mem_ranges=2147483648:2415919103 +memories=system.realview.nvmem system.physmem system.realview.vram +multi_proc=true +num_work_ids=16 +panic_on_oops=true +panic_on_panic=true +phys_addr_range_64=40 +readfile=/work/gem5.ext/tests/halt.sh +reset_addr_64=0 +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[1] + +[system.bridge] +type=Bridge +clk_domain=system.clk_domain +delay=50000 +eventq_index=0 +ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 +req_size=16 +resp_size=16 +master=system.iobus.slave[0] +slave=system.membus.master[0] + +[system.cf0] +type=IdeDisk +children=image +delay=1000000 +driveID=master +eventq_index=0 +image=system.cf0.image + +[system.cf0.image] +type=CowDiskImage +children=child +child=system.cf0.image.child +eventq_index=0 +image_file= +read_only=false +table_size=65536 + +[system.cf0.image.child] +type=RawDiskImage +eventq_index=0 +image_file=/dist/disks/linux-aarch32-ael.img +read_only=true + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu0] +type=TimingSimpleCPU +children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer +branchPred=Null +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dstage2_mmu=system.cpu0.dstage2_mmu +dtb=system.cpu0.dtb +eventq_index=0 +function_trace=false +function_trace_start=0 +interrupts=system.cpu0.interrupts +isa=system.cpu0.isa +istage2_mmu=system.cpu0.istage2_mmu +itb=system.cpu0.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +tracer=system.cpu0.tracer +workload= +dcache_port=system.cpu0.dcache.cpu_side +icache_port=system.cpu0.icache.cpu_side + +[system.cpu0.dcache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=4 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=32768 +system=system +tags=system.cpu0.dcache.tags +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu0.dcache_port +mem_side=system.toL2Bus.slave[1] + +[system.cpu0.dcache.tags] +type=LRU +assoc=4 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=32768 + +[system.cpu0.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb +tlb=system.cpu0.dtb + +[system.cpu0.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu0.dstage2_mmu.stage2_tlb.walker + +[system.cpu0.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.toL2Bus.slave[5] + +[system.cpu0.dtb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu0.dtb.walker + +[system.cpu0.dtb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system +port=system.toL2Bus.slave[3] + +[system.cpu0.icache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=1 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=32768 +system=system +tags=system.cpu0.icache.tags +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu0.icache_port +mem_side=system.toL2Bus.slave[0] + +[system.cpu0.icache.tags] +type=LRU +assoc=1 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=32768 + +[system.cpu0.interrupts] +type=ArmInterrupts +eventq_index=0 + +[system.cpu0.isa] +type=ArmISA +eventq_index=0 +fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=270536963 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=34611729 +id_pfr0=49 +id_pfr1=4113 +midr=1091551472 +pmu=Null +system=system + +[system.cpu0.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb +tlb=system.cpu0.itb + +[system.cpu0.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu0.istage2_mmu.stage2_tlb.walker + +[system.cpu0.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.toL2Bus.slave[4] + +[system.cpu0.itb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu0.itb.walker + +[system.cpu0.itb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system +port=system.toL2Bus.slave[2] + +[system.cpu0.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu1] +type=TimingSimpleCPU +children=dstage2_mmu dtb isa istage2_mmu itb tracer +branchPred=Null +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dstage2_mmu=system.cpu1.dstage2_mmu +dtb=system.cpu1.dtb +eventq_index=0 +function_trace=false +function_trace_start=0 +interrupts=Null +isa=system.cpu1.isa +istage2_mmu=system.cpu1.istage2_mmu +itb=system.cpu1.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=true +system=system +tracer=system.cpu1.tracer +workload= + +[system.cpu1.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb +tlb=system.cpu1.dtb + +[system.cpu1.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu1.dstage2_mmu.stage2_tlb.walker + +[system.cpu1.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system + +[system.cpu1.dtb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu1.dtb.walker + +[system.cpu1.dtb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system + +[system.cpu1.isa] +type=ArmISA +eventq_index=0 +fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=270536963 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=34611729 +id_pfr0=49 +id_pfr1=4113 +midr=1091551472 +pmu=Null +system=system + +[system.cpu1.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb +tlb=system.cpu1.itb + +[system.cpu1.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu1.istage2_mmu.stage2_tlb.walker + +[system.cpu1.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system + +[system.cpu1.itb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu1.itb.walker + +[system.cpu1.itb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system + +[system.cpu1.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.intrctrl] +type=IntrControl +eventq_index=0 +sys=system + +[system.iobus] +type=NoncoherentXBar +clk_domain=system.clk_domain +eventq_index=0 +header_cycles=1 +use_default_range=true +width=8 +default=system.realview.pciconfig.pio +master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side +slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma + +[system.iocache] +type=BaseCache +children=tags +addr_ranges=2147483648:2415919103 +assoc=8 +clk_domain=system.clk_domain +eventq_index=0 +forward_snoops=false +hit_latency=50 +is_top_level=true +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +response_latency=50 +sequential_access=false +size=1024 +system=system +tags=system.iocache.tags +tgts_per_mshr=12 +two_queue=false +write_buffers=8 +cpu_side=system.iobus.master[27] +mem_side=system.membus.slave[3] + +[system.iocache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.clk_domain +eventq_index=0 +hit_latency=50 +sequential_access=false +size=1024 + +[system.l2c] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=20 +is_top_level=false +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=4194304 +system=system +tags=system.l2c.tags +tgts_per_mshr=12 +two_queue=false +write_buffers=8 +cpu_side=system.toL2Bus.master[0] +mem_side=system.membus.slave[2] + +[system.l2c.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=20 +sequential_access=false +size=4194304 + +[system.membus] +type=CoherentXBar +children=badaddr_responder +clk_domain=system.clk_domain +eventq_index=0 +header_cycles=1 +snoop_filter=Null +system=system +use_default_range=false +width=8 +default=system.membus.badaddr_responder.pio +master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port +slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side + +[system.membus.badaddr_responder] +type=IsaFake +clk_domain=system.clk_domain +eventq_index=0 +fake_mem=false +pio_addr=0 +pio_latency=100000 +pio_size=8 +ret_bad_addr=true +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access=warn +pio=system.membus.default + +[system.physmem] +type=DRAMCtrl +IDD0=0.075000 +IDD02=0.000000 +IDD2N=0.050000 +IDD2N2=0.000000 +IDD2P0=0.000000 +IDD2P02=0.000000 +IDD2P1=0.000000 +IDD2P12=0.000000 +IDD3N=0.057000 +IDD3N2=0.000000 +IDD3P0=0.000000 +IDD3P02=0.000000 +IDD3P1=0.000000 +IDD3P12=0.000000 +IDD4R=0.187000 +IDD4R2=0.000000 +IDD4W=0.165000 +IDD4W2=0.000000 +IDD5=0.220000 +IDD52=0.000000 +IDD6=0.000000 +IDD62=0.000000 +VDD=1.500000 +VDD2=0.000000 +activation_limit=4 +addr_mapping=RoRaBaChCo +bank_groups_per_rank=0 +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +eventq_index=0 +in_addr_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +range=2147483648:2415919103 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tBURST=5000 +tCCD_L=0 +tCK=1250 +tCL=13750 +tCS=2500 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tXAW=30000 +tXP=0 +tXPDLL=0 +tXS=0 +tXSDLL=0 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[5] + +[system.realview] +type=RealView +children=aaci_fake cf_ctrl clcd energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake +eventq_index=0 +intrctrl=system.intrctrl +pci_cfg_base=805306368 +pci_cfg_gen_offsets=false +pci_io_base=0 +system=system + +[system.realview.aaci_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=470024192 +pio_latency=100000 +system=system +pio=system.iobus.master[18] + +[system.realview.cf_ctrl] +type=IdeController +BAR0=471465984 +BAR0LegacyIO=true +BAR0Size=256 +BAR1=471466240 +BAR1LegacyIO=true +BAR1Size=4096 +BAR2=1 +BAR2LegacyIO=false +BAR2Size=8 +BAR3=1 +BAR3LegacyIO=false +BAR3Size=4 +BAR4=1 +BAR4LegacyIO=false +BAR4Size=16 +BAR5=1 +BAR5LegacyIO=false +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CapabilityPtr=0 +CardbusCIS=0 +ClassCode=1 +Command=1 +DeviceID=28945 +ExpansionROM=0 +HeaderType=0 +InterruptLine=31 +InterruptPin=1 +LatencyTimer=0 +LegacyIOBase=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 +MaximumLatency=0 +MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 +ProgIF=133 +Revision=0 +Status=640 +SubClassCode=1 +SubsystemID=0 +SubsystemVendorID=0 +VendorID=32902 +clk_domain=system.clk_domain +config_latency=20000 +ctrl_offset=2 +disks= +eventq_index=0 +io_shift=2 +pci_bus=2 +pci_dev=0 +pci_func=0 +pio_latency=30000 +platform=system.realview +system=system +config=system.iobus.master[9] +dma=system.iobus.slave[2] +pio=system.iobus.master[8] + +[system.realview.clcd] +type=Pl111 +amba_id=1315089 +clk_domain=system.clk_domain +enable_capture=true +eventq_index=0 +gic=system.realview.gic +int_num=46 +pio_addr=471793664 +pio_latency=10000 +pixel_clock=41667 +system=system +vnc=system.vncserver +dma=system.iobus.slave[1] +pio=system.iobus.master[4] + +[system.realview.energy_ctrl] +type=EnergyCtrl +clk_domain=system.clk_domain +dvfs_handler=system.dvfs_handler +eventq_index=0 +pio_addr=470286336 +pio_latency=100000 +system=system +pio=system.iobus.master[22] + +[system.realview.ethernet] +type=IGbE +BAR0=0 +BAR0LegacyIO=false +BAR0Size=131072 +BAR1=0 +BAR1LegacyIO=false +BAR1Size=0 +BAR2=0 +BAR2LegacyIO=false +BAR2Size=0 +BAR3=0 +BAR3LegacyIO=false +BAR3Size=0 +BAR4=0 +BAR4LegacyIO=false +BAR4Size=0 +BAR5=0 +BAR5LegacyIO=false +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CapabilityPtr=0 +CardbusCIS=0 +ClassCode=2 +Command=0 +DeviceID=4213 +ExpansionROM=0 +HeaderType=0 +InterruptLine=1 +InterruptPin=1 +LatencyTimer=0 +LegacyIOBase=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 +MaximumLatency=0 +MinimumGrant=255 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 +ProgIF=0 +Revision=0 +Status=0 +SubClassCode=0 +SubsystemID=4104 +SubsystemVendorID=32902 +VendorID=32902 +clk_domain=system.clk_domain +config_latency=20000 +eventq_index=0 +fetch_comp_delay=10000 +fetch_delay=10000 +hardware_address=00:90:00:00:00:01 +pci_bus=0 +pci_dev=0 +pci_func=0 +phy_epid=896 +phy_pid=680 +pio_latency=30000 +platform=system.realview +rx_desc_cache_size=64 +rx_fifo_size=393216 +rx_write_delay=0 +system=system +tx_desc_cache_size=64 +tx_fifo_size=393216 +tx_read_delay=0 +wb_comp_delay=10000 +wb_delay=10000 +config=system.iobus.master[26] +dma=system.iobus.slave[4] +pio=system.iobus.master[25] + +[system.realview.generic_timer] +type=GenericTimer +eventq_index=0 +gic=system.realview.gic +int_num=29 +system=system + +[system.realview.gic] +type=Pl390 +clk_domain=system.clk_domain +cpu_addr=738205696 +cpu_pio_delay=10000 +dist_addr=738201600 +dist_pio_delay=10000 +eventq_index=0 +int_latency=10000 +it_lines=128 +msix_addr=0 +platform=system.realview +system=system +pio=system.membus.master[2] + +[system.realview.hdlcd] +type=HDLcd +amba_id=1314816 +clk_domain=system.clk_domain +enable_capture=true +eventq_index=0 +gic=system.realview.gic +int_num=117 +pio_addr=721420288 +pio_latency=10000 +pixel_clock=7299 +system=system +vnc=system.vncserver +dma=system.membus.slave[0] +pio=system.iobus.master[5] + +[system.realview.ide] +type=IdeController +BAR0=1 +BAR0LegacyIO=false +BAR0Size=8 +BAR1=1 +BAR1LegacyIO=false +BAR1Size=4 +BAR2=1 +BAR2LegacyIO=false +BAR2Size=8 +BAR3=1 +BAR3LegacyIO=false +BAR3Size=4 +BAR4=1 +BAR4LegacyIO=false +BAR4Size=16 +BAR5=1 +BAR5LegacyIO=false +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CapabilityPtr=0 +CardbusCIS=0 +ClassCode=1 +Command=0 +DeviceID=28945 +ExpansionROM=0 +HeaderType=0 +InterruptLine=2 +InterruptPin=2 +LatencyTimer=0 +LegacyIOBase=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 +MaximumLatency=0 +MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 +ProgIF=133 +Revision=0 +Status=640 +SubClassCode=1 +SubsystemID=0 +SubsystemVendorID=0 +VendorID=32902 +clk_domain=system.clk_domain +config_latency=20000 +ctrl_offset=0 +disks=system.cf0 +eventq_index=0 +io_shift=0 +pci_bus=0 +pci_dev=1 +pci_func=0 +pio_latency=30000 +platform=system.realview +system=system +config=system.iobus.master[24] +dma=system.iobus.slave[3] +pio=system.iobus.master[23] + +[system.realview.kmi0] +type=Pl050 +amba_id=1314896 +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +int_delay=1000000 +int_num=44 +is_mouse=false +pio_addr=470155264 +pio_latency=100000 +system=system +vnc=system.vncserver +pio=system.iobus.master[6] + +[system.realview.kmi1] +type=Pl050 +amba_id=1314896 +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +int_delay=1000000 +int_num=45 +is_mouse=true +pio_addr=470220800 +pio_latency=100000 +system=system +vnc=system.vncserver +pio=system.iobus.master[7] + +[system.realview.l2x0_fake] +type=IsaFake +clk_domain=system.clk_domain +eventq_index=0 +fake_mem=false +pio_addr=739246080 +pio_latency=100000 +pio_size=4095 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[12] + +[system.realview.lan_fake] +type=IsaFake +clk_domain=system.clk_domain +eventq_index=0 +fake_mem=false +pio_addr=436207616 +pio_latency=100000 +pio_size=65535 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[19] + +[system.realview.local_cpu_timer] +type=CpuLocalTimer +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +int_num_timer=29 +int_num_watchdog=30 +pio_addr=738721792 +pio_latency=100000 +system=system +pio=system.membus.master[3] + +[system.realview.mmc_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=470089728 +pio_latency=100000 +system=system +pio=system.iobus.master[21] + +[system.realview.nvmem] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=false +eventq_index=0 +in_addr_map=true +latency=30000 +latency_var=0 +null=false +range=0:67108863 +port=system.membus.master[1] + +[system.realview.pciconfig] +type=PciConfigAll +bus=0 +clk_domain=system.clk_domain +eventq_index=0 +pio_addr=0 +pio_latency=30000 +platform=system.realview +size=268435456 +system=system +pio=system.iobus.default + +[system.realview.realview_io] +type=RealViewCtrl +clk_domain=system.clk_domain +eventq_index=0 +idreg=35979264 +pio_addr=469827584 +pio_latency=100000 +proc_id0=335544320 +proc_id1=335544320 +system=system +pio=system.iobus.master[1] + +[system.realview.rtc] +type=PL031 +amba_id=3412017 +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +int_delay=100000 +int_num=36 +pio_addr=471269376 +pio_latency=100000 +system=system +time=Thu Jan 1 00:00:00 2009 +pio=system.iobus.master[10] + +[system.realview.sp810_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=true +pio_addr=469893120 +pio_latency=100000 +system=system +pio=system.iobus.master[16] + +[system.realview.timer0] +type=Sp804 +amba_id=1316868 +clk_domain=system.clk_domain +clock0=1000000 +clock1=1000000 +eventq_index=0 +gic=system.realview.gic +int_num0=34 +int_num1=34 +pio_addr=470876160 +pio_latency=100000 +system=system +pio=system.iobus.master[2] + +[system.realview.timer1] +type=Sp804 +amba_id=1316868 +clk_domain=system.clk_domain +clock0=1000000 +clock1=1000000 +eventq_index=0 +gic=system.realview.gic +int_num0=35 +int_num1=35 +pio_addr=470941696 +pio_latency=100000 +system=system +pio=system.iobus.master[3] + +[system.realview.uart] +type=Pl011 +clk_domain=system.clk_domain +end_on_eot=false +eventq_index=0 +gic=system.realview.gic +int_delay=100000 +int_num=37 +pio_addr=470351872 +pio_latency=100000 +platform=system.realview +system=system +terminal=system.terminal +pio=system.iobus.master[0] + +[system.realview.uart1_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=470417408 +pio_latency=100000 +system=system +pio=system.iobus.master[13] + +[system.realview.uart2_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=470482944 +pio_latency=100000 +system=system +pio=system.iobus.master[14] + +[system.realview.uart3_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=470548480 +pio_latency=100000 +system=system +pio=system.iobus.master[15] + +[system.realview.usb_fake] +type=IsaFake +clk_domain=system.clk_domain +eventq_index=0 +fake_mem=false +pio_addr=452984832 +pio_latency=100000 +pio_size=131071 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[20] + +[system.realview.vgic] +type=VGic +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +hv_addr=738213888 +pio_delay=10000 +platform=system.realview +ppint=25 +system=system +vcpu_addr=738222080 +pio=system.membus.master[4] + +[system.realview.vram] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=false +eventq_index=0 +in_addr_map=true +latency=30000 +latency_var=0 +null=false +range=402653184:436207615 +port=system.iobus.master[11] + +[system.realview.watchdog_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=470745088 +pio_latency=100000 +system=system +pio=system.iobus.master[17] + +[system.terminal] +type=Terminal +eventq_index=0 +intr_control=system.intrctrl +number=0 +output=true +port=3456 + +[system.toL2Bus] +type=CoherentXBar +clk_domain=system.cpu_clk_domain +eventq_index=0 +header_cycles=1 +snoop_filter=Null +system=system +use_default_range=false +width=8 +master=system.l2c.cpu_side +slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port + +[system.vncserver] +type=VncServer +eventq_index=0 +frame_capture=false +number=0 +port=5900 + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simerr b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simerr new file mode 100755 index 000000000..067647ddd --- /dev/null +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simerr @@ -0,0 +1,69 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) +warn: Sockets disabled, not accepting vnc client connections +warn: Sockets disabled, not accepting terminal connections +warn: Sockets disabled, not accepting gdb connections +warn: Existing EnergyCtrl, but no enabled DVFSHandler found. +warn: Not doing anything for miscreg ACTLR +warn: Not doing anything for write of miscreg ACTLR +warn: The clidr register always reports 0 caches. +warn: clidr LoUIS field of 0b001 to match current ARM implementations. +warn: The csselr register isn't implemented. +warn: instruction 'mcr dccmvau' unimplemented +warn: instruction 'mcr icimvau' unimplemented +warn: instruction 'mcr bpiallis' unimplemented +warn: instruction 'mcr icialluis' unimplemented +warn: instruction 'mcr dccimvac' unimplemented +warn: Tried to read RealView I/O at offset 0x60 that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4] +warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4] +warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0] +warn: Returning zero for read from miscreg pmcr +warn: Ignoring write to miscreg pmcntenclr +warn: Ignoring write to miscreg pmintenclr +warn: Ignoring write to miscreg pmovsr +warn: Ignoring write to miscreg pmcr +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simout new file mode 100755 index 000000000..28734ef64 --- /dev/null +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simout @@ -0,0 +1,10 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Oct 31 2014 10:01:44 +gem5 started Oct 31 2014 11:48:18 +gem5 executing on u200540-lin +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-timing -re /work/gem5.ext/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-timing +Global frequency set at 1000000000000 ticks per second + 0: system.cpu0.isa: ISA system set to: 0x4989680 0x4989680 + 0: system.cpu1.isa: ISA system set to: 0x4989680 0x4989680 diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt new file mode 100644 index 000000000..7478799f2 --- /dev/null +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt @@ -0,0 +1,1915 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 2.903641 # Number of seconds simulated +sim_ticks 2903640922500 # Number of ticks simulated +final_tick 2903640922500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 705602 # Simulator instruction rate (inst/s) +host_op_rate 850741 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 18218787173 # Simulator tick rate (ticks/s) +host_mem_usage 616688 # Number of bytes of host memory used +host_seconds 159.38 # Real time elapsed on the host +sim_insts 112456119 # Number of instructions simulated +sim_ops 135587804 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu0.dtb.walker 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 582564 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 3808480 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 602944 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5025476 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory +system.physmem.bytes_read::total 10021000 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 582564 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 602944 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1185508 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7434688 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 17516 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 8 # Number of bytes written to this memory +system.physmem.bytes_written::total 7452212 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 17556 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 60026 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 9421 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 78524 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory +system.physmem.num_reads::total 165551 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 116167 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory +system.physmem.num_writes::total 120548 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 66 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 44 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 200632 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1311622 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 88 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 207651 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1730750 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 331 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3451184 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 200632 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 207651 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 408283 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2560471 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6032 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2566506 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2560471 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 66 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 44 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 200632 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1317655 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 88 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 207651 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1730753 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 331 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6017690 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 165551 # Number of read requests accepted +system.physmem.writeReqs 156772 # Number of write requests accepted +system.physmem.readBursts 165551 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 156772 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10588736 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6528 # Total number of bytes read from write queue +system.physmem.bytesWritten 8522624 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10021000 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 9770548 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 102 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 23601 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4489 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 9899 # Per bank write bursts +system.physmem.perBankRdBursts::1 9526 # Per bank write bursts +system.physmem.perBankRdBursts::2 9759 # Per bank write bursts +system.physmem.perBankRdBursts::3 9793 # Per bank write bursts +system.physmem.perBankRdBursts::4 18999 # Per bank write bursts +system.physmem.perBankRdBursts::5 10033 # Per bank write bursts +system.physmem.perBankRdBursts::6 10462 # Per bank write bursts +system.physmem.perBankRdBursts::7 10803 # Per bank write bursts +system.physmem.perBankRdBursts::8 9925 # Per bank write bursts +system.physmem.perBankRdBursts::9 10243 # Per bank write bursts +system.physmem.perBankRdBursts::10 9858 # Per bank write bursts +system.physmem.perBankRdBursts::11 9250 # Per bank write bursts +system.physmem.perBankRdBursts::12 9247 # Per bank write bursts +system.physmem.perBankRdBursts::13 9475 # Per bank write bursts +system.physmem.perBankRdBursts::14 9028 # Per bank write bursts +system.physmem.perBankRdBursts::15 9149 # Per bank write bursts +system.physmem.perBankWrBursts::0 8258 # Per bank write bursts +system.physmem.perBankWrBursts::1 8244 # Per bank write bursts +system.physmem.perBankWrBursts::2 8572 # Per bank write bursts +system.physmem.perBankWrBursts::3 8149 # Per bank write bursts +system.physmem.perBankWrBursts::4 8563 # Per bank write bursts +system.physmem.perBankWrBursts::5 8536 # Per bank write bursts +system.physmem.perBankWrBursts::6 8718 # Per bank write bursts +system.physmem.perBankWrBursts::7 9117 # Per bank write bursts +system.physmem.perBankWrBursts::8 8657 # Per bank write bursts +system.physmem.perBankWrBursts::9 8771 # Per bank write bursts +system.physmem.perBankWrBursts::10 8610 # Per bank write bursts +system.physmem.perBankWrBursts::11 7990 # Per bank write bursts +system.physmem.perBankWrBursts::12 7949 # Per bank write bursts +system.physmem.perBankWrBursts::13 7964 # Per bank write bursts +system.physmem.perBankWrBursts::14 7531 # Per bank write bursts +system.physmem.perBankWrBursts::15 7537 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 32 # Number of times write queue was full causing retry +system.physmem.totGap 2903640597500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 9558 # Read request sizes (log2) +system.physmem.readPktSize::3 14 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 155979 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 4381 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 152391 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 164623 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 542 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 272 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 178 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 160 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1636 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1852 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5271 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5453 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5489 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5477 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5778 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6926 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5746 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7269 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6043 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6071 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7760 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6386 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5989 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6226 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1272 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1286 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 2214 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1803 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1883 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 2499 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1872 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1797 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1557 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1902 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1747 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1424 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1057 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 786 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 394 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 308 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 312 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 191 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 40 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 57876 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 330.211072 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 191.290947 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 346.940345 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 20714 35.79% 35.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14256 24.63% 60.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5208 9.00% 69.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3123 5.40% 74.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2440 4.22% 79.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1489 2.57% 81.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1071 1.85% 83.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1111 1.92% 85.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8464 14.62% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 57876 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5262 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 31.441087 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 579.786182 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 5260 99.96% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::40960-43007 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 5262 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5262 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 25.307108 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.699141 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 47.946490 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-15 45 0.86% 0.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 4897 93.06% 93.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 79 1.50% 95.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 16 0.30% 95.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 14 0.27% 95.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 19 0.36% 96.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 31 0.59% 96.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 27 0.51% 97.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 13 0.25% 97.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 8 0.15% 97.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 3 0.06% 97.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 23 0.44% 98.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 14 0.27% 98.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 10 0.19% 98.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-239 3 0.06% 98.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-255 3 0.06% 98.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-271 3 0.06% 98.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-287 4 0.08% 99.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 8 0.15% 99.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 4 0.08% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 3 0.06% 99.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 5 0.10% 99.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 8 0.15% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-383 1 0.02% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-399 1 0.02% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::416-431 1 0.02% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::432-447 1 0.02% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::464-479 1 0.02% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::496-511 3 0.06% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-527 1 0.02% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::528-543 3 0.06% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-559 3 0.06% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::560-575 1 0.02% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::608-623 1 0.02% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::656-671 1 0.02% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::672-687 1 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::688-703 1 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::720-735 2 0.04% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5262 # Writes before turning the bus around for reads +system.physmem.totQLat 1437662314 # Total ticks spent queuing +system.physmem.totMemAccLat 4539831064 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 827245000 # Total ticks spent in databus transfers +system.physmem.avgQLat 8689.46 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 27439.46 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.65 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.94 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.45 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.36 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 0.05 # Data bus utilization in percentage +system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 10.50 # Average write queue length when enqueuing +system.physmem.readRowHits 136363 # Number of row buffer hits during reads +system.physmem.writeRowHits 104375 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.42 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.38 # Row buffer hit rate for writes +system.physmem.avgGap 9008480.93 # Average gap between requests +system.physmem.pageHitRate 80.62 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 229453560 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 125197875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 696337200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 441657360 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 189651686640 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 86953063950 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1665909868500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1944007265085 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.506799 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2771232360210 # Time in different power states +system.physmem_0.memoryStateTime::REF 96958940000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 35449523540 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 208089000 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 113540625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 594157200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 421258320 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 189651686640 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 84877892595 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1667730194250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1943596818630 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.365444 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2774279366726 # Time in different power states +system.physmem_1.memoryStateTime::REF 96958940000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 32402517024 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 7 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s) +system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). +system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). +system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. +system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. +system.cf0.dma_write_txs 631 # Number of DMA write transactions. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.dtb.walker.walks 6899 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 6899 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 2220 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 4679 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 6899 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 6899 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 6899 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 5841 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 12315.228557 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 10506.489584 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 6688.963614 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-16383 4458 76.32% 76.32% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::16384-32767 1381 23.64% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::81920-98303 1 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 5841 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 937449500 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 937449500 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 937449500 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 3645 62.40% 62.40% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 2196 37.60% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 5841 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 6899 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 6899 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 5841 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 5841 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 12740 # Table walker requests started/completed, data/inst +system.cpu0.dtb.inst_hits 0 # ITB inst hits +system.cpu0.dtb.inst_misses 0 # ITB inst misses +system.cpu0.dtb.read_hits 12462635 # DTB read hits +system.cpu0.dtb.read_misses 5988 # DTB read misses +system.cpu0.dtb.write_hits 9832923 # DTB write hits +system.cpu0.dtb.write_misses 911 # DTB write misses +system.cpu0.dtb.flush_tlb 2938 # Number of times complete TLB was flushed +system.cpu0.dtb.flush_tlb_mva 496 # Number of times TLB was flushed by MVA +system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 4660 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 940 # Number of TLB faults due to prefetch +system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu0.dtb.perms_faults 240 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 12468623 # DTB read accesses +system.cpu0.dtb.write_accesses 9833834 # DTB write accesses +system.cpu0.dtb.inst_accesses 0 # ITB inst accesses +system.cpu0.dtb.hits 22295558 # DTB hits +system.cpu0.dtb.misses 6899 # DTB misses +system.cpu0.dtb.accesses 22302457 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.itb.walker.walks 3577 # Table walker walks requested +system.cpu0.itb.walker.walksShort 3577 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walksShortTerminationLevel::Level1 835 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 2742 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 3577 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 3577 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 3577 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 2726 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 12637.197359 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 10746.267304 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 6704.748097 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-8191 633 23.22% 23.22% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::8192-16383 1408 51.65% 74.87% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-24575 683 25.06% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::81920-90111 1 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 2726 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 937122000 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 937122000 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 937122000 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 1891 69.37% 69.37% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 835 30.63% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2726 # Table walker page sizes translated +system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3577 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3577 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2726 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2726 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 6303 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 58414032 # ITB inst hits +system.cpu0.itb.inst_misses 3577 # ITB inst misses +system.cpu0.itb.read_hits 0 # DTB read hits +system.cpu0.itb.read_misses 0 # DTB read misses +system.cpu0.itb.write_hits 0 # DTB write hits +system.cpu0.itb.write_misses 0 # DTB write misses +system.cpu0.itb.flush_tlb 2938 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb_mva 496 # Number of times TLB was flushed by MVA +system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 2760 # Number of entries that have been flushed from TLB +system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.read_accesses 0 # DTB read accesses +system.cpu0.itb.write_accesses 0 # DTB write accesses +system.cpu0.itb.inst_accesses 58417609 # ITB inst accesses +system.cpu0.itb.hits 58414032 # DTB hits +system.cpu0.itb.misses 3577 # DTB misses +system.cpu0.itb.accesses 58417609 # DTB accesses +system.cpu0.numCycles 2904051621 # number of cpu cycles simulated +system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu0.committedInsts 56844590 # Number of instructions committed +system.cpu0.committedOps 68476862 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 60556147 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 5891 # Number of float alu accesses +system.cpu0.num_func_calls 5072041 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 7664286 # number of instructions that are conditional controls +system.cpu0.num_int_insts 60556147 # number of integer instructions +system.cpu0.num_fp_insts 5891 # number of float instructions +system.cpu0.num_int_register_reads 110162183 # number of times the integer registers were read +system.cpu0.num_int_register_writes 41899351 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 4609 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 1284 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 247668564 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 26017746 # number of times the CC registers were written +system.cpu0.num_mem_refs 22952183 # number of memory refs +system.cpu0.num_load_insts 12628752 # Number of load instructions +system.cpu0.num_store_insts 10323431 # Number of store instructions +system.cpu0.num_idle_cycles 2690582406.498001 # Number of idle cycles +system.cpu0.num_busy_cycles 213469214.501999 # Number of busy cycles +system.cpu0.not_idle_fraction 0.073507 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.926493 # Percentage of idle cycles +system.cpu0.Branches 13135796 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2207 0.00% 0.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 47055843 67.15% 67.15% # Class of executed instruction +system.cpu0.op_class::IntMult 59396 0.08% 67.24% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 67.24% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 67.24% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 67.24% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 67.24% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 67.24% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 67.24% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 67.24% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 67.24% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 67.24% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 67.24% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 67.24% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 67.24% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 67.24% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 67.24% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 67.24% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 67.24% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 67.24% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 67.24% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 67.24% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.24% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.24% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.24% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.24% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 4431 0.01% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::MemRead 12628752 18.02% 85.27% # Class of executed instruction +system.cpu0.op_class::MemWrite 10323431 14.73% 100.00% # Class of executed instruction +system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu0.op_class::total 70074060 # Class of executed instruction +system.cpu0.kern.inst.arm 0 # number of arm instructions executed +system.cpu0.kern.inst.quiesce 3032 # number of quiesce instructions executed +system.cpu0.dcache.tags.replacements 821716 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.827808 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 43234238 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 822228 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 52.581812 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 1008982250 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 377.484524 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 134.343284 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.737274 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.262389 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.999664 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 373 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 82 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 177115546 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 177115546 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 11742107 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 11368313 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 23110420 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 9438605 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 9386535 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 18825140 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 200385 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 191808 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 392193 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 230728 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 212742 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 443470 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 239351 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 220930 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 460281 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 21180712 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 20754848 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 41935560 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 21381097 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 20946656 # number of overall hits +system.cpu0.dcache.overall_hits::total 42327753 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 202379 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 199779 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 402158 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 143306 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 155169 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 298475 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 60388 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu1.data 58192 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 118580 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 11633 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 10971 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 22604 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 345685 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 354948 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 700633 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 406073 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 413140 # number of overall misses +system.cpu0.dcache.overall_misses::total 819213 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 2998718242 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2978169130 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5976887372 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5523492960 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 6886936529 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 12410429489 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 144593750 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 135344000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 279937750 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 164000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 164000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 8522211202 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 9865105659 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 18387316861 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 8522211202 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 9865105659 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 18387316861 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 11944486 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 11568092 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 23512578 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 9581911 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 9541704 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 19123615 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 260773 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 250000 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 510773 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 242361 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 223713 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 466074 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 239353 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 220930 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 460283 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 21526397 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 21109796 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 42636193 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 21787170 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 21359796 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 43146966 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.016943 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.017270 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.017104 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.014956 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.016262 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.015608 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.231573 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.232768 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.232158 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.047999 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.049041 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.048499 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000008 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.016059 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.016814 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.016433 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.018638 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.019342 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.018987 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14817.338963 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14907.318237 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14862.037736 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38543.347522 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 44383.456290 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 41579.460554 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12429.618327 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12336.523562 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12384.434171 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 82000 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 82000 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 24653.112522 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 27793.101127 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 26243.863565 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 20986.894480 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 23878.360021 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 22445.098968 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 57 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 19 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 3 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.dcache.fast_writes 0 # number of fast writes performed +system.cpu0.dcache.cache_copies 0 # number of cache copies performed +system.cpu0.dcache.writebacks::writebacks 687030 # number of writebacks +system.cpu0.dcache.writebacks::total 687030 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 287 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 373 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 660 # number of ReadReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 7066 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 7026 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14092 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 287 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 373 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 660 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 287 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 373 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 660 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 202092 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 199406 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 401498 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 143306 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 155169 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 298475 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 59468 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 57033 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 116501 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 4567 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 3945 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8512 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 345398 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 354575 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 699973 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 404866 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 411608 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 816474 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2687850000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2671783250 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5359633250 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5284681040 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 6621405971 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11906087011 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 749127008 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 719245636 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1468372644 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 55884250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 49619250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 105503500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 161000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 161000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7972531040 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 9293189221 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 17265720261 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8721658048 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 10012434857 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 18734092905 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2822172000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3011105500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5833277500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2259926000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2253271000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4513197000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5082098000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 5264376500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10346474500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016919 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.017238 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017076 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.014956 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.016262 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.015608 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.228045 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.228132 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.228088 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.018844 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.017634 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.018263 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000008 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016045 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.016797 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.016417 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018583 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.019270 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.018923 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13300.130634 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13398.710420 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13349.090780 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36876.900060 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 42672.221713 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39889.729495 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 12597.144817 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 12611.043361 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 12603.948842 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12236.533830 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12577.756654 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12394.678102 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 80500 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 80500 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23082.157511 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 26209.375227 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24666.266072 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21542.085648 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24325.170689 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22945.118773 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.icache.tags.replacements 1701384 # number of replacements +system.cpu0.icache.tags.tagsinuse 510.734068 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 113852033 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1701896 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 66.897174 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 25697074250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 399.197143 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 111.536926 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.779682 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.217846 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.997527 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 205 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 251 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 10 # Occupied blocks per task id +system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.icache.tags.tag_accesses 117255837 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 117255837 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 57557381 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 56294652 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 113852033 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 57557381 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 56294652 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 113852033 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 57557381 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 56294652 # number of overall hits +system.cpu0.icache.overall_hits::total 113852033 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 856651 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 845251 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1701902 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 856651 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 845251 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1701902 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 856651 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 845251 # number of overall misses +system.cpu0.icache.overall_misses::total 1701902 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11730914498 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 11646451999 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 23377366497 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 11730914498 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 11646451999 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 23377366497 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 11730914498 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 11646451999 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 23377366497 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 58414032 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 57139903 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 115553935 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 58414032 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 57139903 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 115553935 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 58414032 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 57139903 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 115553935 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014665 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.014793 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014728 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014665 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.014793 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014728 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014665 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.014793 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014728 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13693.924945 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13778.690589 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13736.023870 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13693.924945 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13778.690589 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13736.023870 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13693.924945 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13778.690589 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13736.023870 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.icache.fast_writes 0 # number of fast writes performed +system.cpu0.icache.cache_copies 0 # number of cache copies performed +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 856651 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 845251 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1701902 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 856651 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 845251 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1701902 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 856651 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 845251 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1701902 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10442855002 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 10375133501 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 20817988503 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10442855002 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 10375133501 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 20817988503 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10442855002 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 10375133501 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 20817988503 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 677067750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 677067750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 677067750 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 677067750 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014665 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014793 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014728 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014665 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.014793 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.014728 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014665 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.014793 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.014728 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12190.326051 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12274.618428 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12232.189928 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12190.326051 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12274.618428 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12232.189928 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12190.326051 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12274.618428 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12232.189928 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.dtb.walker.walks 6646 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 6646 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 1848 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 4797 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 1 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 6645 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 6645 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 6645 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 5540 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 12435.469314 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 10508.495094 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 6654.820556 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-8191 1371 24.75% 24.75% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::8192-16383 2761 49.84% 74.58% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-24575 1405 25.36% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::81920-90111 3 0.05% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 5540 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples -586099820 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 2.706592 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::gmean inf # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 1000233500 -170.66% -170.66% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::1 -1586333320 270.66% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total -586099820 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 3714 67.05% 67.05% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 1825 32.95% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 5539 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 6646 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 6646 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 5539 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5539 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 12185 # Table walker requests started/completed, data/inst +system.cpu1.dtb.inst_hits 0 # ITB inst hits +system.cpu1.dtb.inst_misses 0 # ITB inst misses +system.cpu1.dtb.read_hits 12057381 # DTB read hits +system.cpu1.dtb.read_misses 5757 # DTB read misses +system.cpu1.dtb.write_hits 9774636 # DTB write hits +system.cpu1.dtb.write_misses 889 # DTB write misses +system.cpu1.dtb.flush_tlb 2932 # Number of times complete TLB was flushed +system.cpu1.dtb.flush_tlb_mva 421 # Number of times TLB was flushed by MVA +system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 4087 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 1001 # Number of TLB faults due to prefetch +system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu1.dtb.perms_faults 205 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 12063138 # DTB read accesses +system.cpu1.dtb.write_accesses 9775525 # DTB write accesses +system.cpu1.dtb.inst_accesses 0 # ITB inst accesses +system.cpu1.dtb.hits 21832017 # DTB hits +system.cpu1.dtb.misses 6646 # DTB misses +system.cpu1.dtb.accesses 21838663 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.itb.walker.walks 3230 # Table walker walks requested +system.cpu1.itb.walker.walksShort 3230 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 673 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2557 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 3230 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 3230 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 3230 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 2426 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 12666.941467 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 10866.952957 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 6275.492791 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::2048-4095 541 22.30% 22.30% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::10240-12287 673 27.74% 50.04% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-14335 619 25.52% 75.56% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::20480-22527 528 21.76% 97.32% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::22528-24575 65 2.68% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 2426 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 1000198000 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 1000198000 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 1000198000 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 1753 72.26% 72.26% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 673 27.74% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 2426 # Table walker page sizes translated +system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 3230 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 3230 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2426 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2426 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 5656 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 57139903 # ITB inst hits +system.cpu1.itb.inst_misses 3230 # ITB inst misses +system.cpu1.itb.read_hits 0 # DTB read hits +system.cpu1.itb.read_misses 0 # DTB read misses +system.cpu1.itb.write_hits 0 # DTB write hits +system.cpu1.itb.write_misses 0 # DTB write misses +system.cpu1.itb.flush_tlb 2932 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb_mva 421 # Number of times TLB was flushed by MVA +system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 2427 # Number of entries that have been flushed from TLB +system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.read_accesses 0 # DTB read accesses +system.cpu1.itb.write_accesses 0 # DTB write accesses +system.cpu1.itb.inst_accesses 57143133 # ITB inst accesses +system.cpu1.itb.hits 57139903 # DTB hits +system.cpu1.itb.misses 3230 # DTB misses +system.cpu1.itb.accesses 57143133 # DTB accesses +system.cpu1.numCycles 2903230224 # number of cpu cycles simulated +system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu1.committedInsts 55611529 # Number of instructions committed +system.cpu1.committedOps 67110942 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 59336824 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 5270 # Number of float alu accesses +system.cpu1.num_func_calls 4819801 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 7566653 # number of instructions that are conditional controls +system.cpu1.num_int_insts 59336824 # number of integer instructions +system.cpu1.num_fp_insts 5270 # number of float instructions +system.cpu1.num_int_register_reads 107900734 # number of times the integer registers were read +system.cpu1.num_int_register_writes 40745080 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 3840 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 1432 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 242074272 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 25879956 # number of times the CC registers were written +system.cpu1.num_mem_refs 22456627 # number of memory refs +system.cpu1.num_load_insts 12214155 # Number of load instructions +system.cpu1.num_store_insts 10242472 # Number of store instructions +system.cpu1.num_idle_cycles 2696428184.778518 # Number of idle cycles +system.cpu1.num_busy_cycles 206802039.221482 # Number of busy cycles +system.cpu1.not_idle_fraction 0.071232 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.928768 # Percentage of idle cycles +system.cpu1.Branches 12781357 # Number of branches fetched +system.cpu1.op_class::No_OpClass 130 0.00% 0.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 46119057 67.20% 67.20% # Class of executed instruction +system.cpu1.op_class::IntMult 54779 0.08% 67.28% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 67.28% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 67.28% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 67.28% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 67.28% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 67.28% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 67.28% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 67.28% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 67.28% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 67.28% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 67.28% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 67.28% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 67.28% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 67.28% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 67.28% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 67.28% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 67.28% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 67.28% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 67.28% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 67.28% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 67.28% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 67.28% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 67.28% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 67.28% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 4036 0.01% 67.28% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 67.28% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 67.28% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 67.28% # Class of executed instruction +system.cpu1.op_class::MemRead 12214155 17.80% 85.08% # Class of executed instruction +system.cpu1.op_class::MemWrite 10242472 14.92% 100.00% # Class of executed instruction +system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu1.op_class::total 68634629 # Class of executed instruction +system.cpu1.kern.inst.arm 0 # number of arm instructions executed +system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed +system.iobus.trans_dist::ReadReq 30183 # Transaction distribution +system.iobus.trans_dist::ReadResp 30183 # Transaction distribution +system.iobus.trans_dist::WriteReq 59014 # Transaction distribution +system.iobus.trans_dist::WriteResp 22790 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72916 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72916 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 178394 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2480229 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 38469000 # Layer occupancy (ticks) +system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks) +system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) +system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) +system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks) +system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) +system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks) +system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) +system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) +system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) +system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) +system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer27.occupancy 198848287 # Layer occupancy (ticks) +system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer3.occupancy 36807005 # Layer occupancy (ticks) +system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iocache.tags.replacements 36424 # number of replacements +system.iocache.tags.tagsinuse 1.134606 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 299121172000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.134606 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.070913 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.070913 # Average percentage of cache occupancy +system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id +system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id +system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id +system.iocache.tags.tag_accesses 328122 # Number of tag accesses +system.iocache.tags.data_accesses 328122 # Number of data accesses +system.iocache.ReadReq_misses::realview.ide 234 # number of ReadReq misses +system.iocache.ReadReq_misses::total 234 # number of ReadReq misses +system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses +system.iocache.demand_misses::realview.ide 234 # number of demand (read+write) misses +system.iocache.demand_misses::total 234 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 234 # number of overall misses +system.iocache.overall_misses::total 234 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 29267377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 29267377 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6633096905 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 6633096905 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ide 29267377 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 29267377 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 29267377 # number of overall miss cycles +system.iocache.overall_miss_latency::total 29267377 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.demand_accesses::realview.ide 234 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 234 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 234 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 234 # number of overall (read+write) accesses +system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses +system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses +system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses +system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses +system.iocache.ReadReq_avg_miss_latency::realview.ide 125074.260684 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 125074.260684 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183113.320036 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 183113.320036 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 125074.260684 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 125074.260684 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 125074.260684 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 125074.260684 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 22198 # number of cycles access was blocked +system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3387 # number of cycles access was blocked +system.iocache.blocked::no_targets 0 # number of cycles access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.553882 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.iocache.fast_writes 0 # number of fast writes performed +system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.writebacks::writebacks 36190 # number of writebacks +system.iocache.writebacks::total 36190 # number of writebacks +system.iocache.ReadReq_mshr_misses::realview.ide 234 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 234 # number of ReadReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 36224 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::total 36224 # number of WriteInvalidateReq MSHR misses +system.iocache.demand_mshr_misses::realview.ide 234 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 234 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 234 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 234 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 16965377 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 16965377 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4749438915 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4749438915 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 16965377 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 16965377 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 16965377 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 16965377 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72501.611111 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 72501.611111 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131113.044252 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131113.044252 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 72501.611111 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 72501.611111 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 72501.611111 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 72501.611111 # average overall mshr miss latency +system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2c.tags.replacements 86345 # number of replacements +system.l2c.tags.tagsinuse 64916.534496 # Cycle average of tags in use +system.l2c.tags.total_refs 2772933 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 151598 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 18.291356 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 50295.187878 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.860187 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.965052 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4502.634002 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2814.628972 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 1.894234 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 5158.115832 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2140.248339 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.767444 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000044 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000015 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.068705 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.042948 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000029 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.078707 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.032658 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.990548 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65248 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 12 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 27 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2139 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 6724 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 56346 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.995605 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 26318997 # Number of tag accesses +system.l2c.tags.data_accesses 26318997 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 6505 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 3514 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 848098 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 260151 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 6217 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 3258 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 835810 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 254237 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2217790 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 687030 # number of Writeback hits +system.l2c.Writeback_hits::total 687030 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 16 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 13 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 29 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 87471 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 80339 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 167810 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 6505 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 3514 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 848098 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 347622 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 6217 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 3258 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 835810 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 334576 # number of demand (read+write) hits +system.l2c.demand_hits::total 2385600 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 6505 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 3514 # number of overall hits +system.l2c.overall_hits::cpu0.inst 848098 # number of overall hits +system.l2c.overall_hits::cpu0.data 347622 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 6217 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 3258 # number of overall hits +system.l2c.overall_hits::cpu1.inst 835810 # number of overall hits +system.l2c.overall_hits::cpu1.data 334576 # number of overall hits +system.l2c.overall_hits::total 2385600 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 3 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 8541 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 5976 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 4 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 9421 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 6147 # number of ReadReq misses +system.l2c.ReadReq_misses::total 30094 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 1338 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 1365 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2703 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 2 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 54481 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 73452 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 127933 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 3 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 8541 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 60457 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 4 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 9421 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 79599 # number of demand (read+write) misses +system.l2c.demand_misses::total 158027 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 3 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses +system.l2c.overall_misses::cpu0.inst 8541 # number of overall misses +system.l2c.overall_misses::cpu0.data 60457 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 4 # number of overall misses +system.l2c.overall_misses::cpu1.inst 9421 # number of overall misses +system.l2c.overall_misses::cpu1.data 79599 # number of overall misses +system.l2c.overall_misses::total 158027 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 261750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.itb.walker 166000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 681157002 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 494631258 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 330000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 753847500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 510531136 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 2440924646 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 341989 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 434486 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 776475 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 159000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 159000 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 4180870378 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 5579789336 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 9760659714 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 261750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 166000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 681157002 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 4675501636 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 330000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 753847500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 6090320472 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 12201584360 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 261750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 166000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 681157002 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 4675501636 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 330000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 753847500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 6090320472 # number of overall miss cycles +system.l2c.overall_miss_latency::total 12201584360 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 6508 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 3516 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 856639 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 266127 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 6221 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 3258 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 845231 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 260384 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2247884 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 687030 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 687030 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 1354 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 1378 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 2732 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 2 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 141952 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 153791 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 295743 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 6508 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 3516 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 856639 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 408079 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 6221 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 3258 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 845231 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 414175 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2543627 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 6508 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 3516 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 856639 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 408079 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 6221 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 3258 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 845231 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 414175 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2543627 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000461 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000569 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.009970 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.022455 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000643 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.011146 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.023607 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.013388 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.988183 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.990566 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.989385 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.383799 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.477609 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.432582 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000461 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000569 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.009970 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.148150 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000643 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.011146 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.192187 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.062127 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000461 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000569 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.009970 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.148150 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000643 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.011146 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.192187 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.062127 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 87250 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 83000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 79751.434492 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 82769.621486 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 82500 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 80017.779429 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 83053.706849 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 81110.010168 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 255.597160 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 318.304762 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 287.264151 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 79500 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 79500 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 76739.971329 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 75965.111039 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 76295.089727 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 87250 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 83000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 79751.434492 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 77335.984849 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 82500 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 80017.779429 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 76512.524931 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 77212.023009 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 87250 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 83000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 79751.434492 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 77335.984849 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 82500 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 80017.779429 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 76512.524931 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 77212.023009 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked::no_targets 0 # number of cycles access was blocked +system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.writebacks::writebacks 79977 # number of writebacks +system.l2c.writebacks::total 79977 # number of writebacks +system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 3 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 8541 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 5976 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 4 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 9421 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 6147 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 30094 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 1338 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 1365 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 2703 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 2 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 54481 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 73452 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 127933 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 3 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 8541 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 60457 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 4 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 9421 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 79599 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 158027 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 3 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 8541 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 60457 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 4 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 9421 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 79599 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 158027 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 223750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 141000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 574142498 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 419922242 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 280000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 635806000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 433639364 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 2064154854 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 23826338 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 24325865 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 48152203 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 135000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 135000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3498745622 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4660357664 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 8159103286 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 223750 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 141000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 574142498 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 3918667864 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 280000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 635806000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 5093997028 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 10223258140 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 223750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 141000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 574142498 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 3918667864 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 280000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 635806000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 5093997028 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 10223258140 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 546237750 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2603822250 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2793047000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 5943107000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2054472000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 2099890500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 4154362500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 546237750 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 4658294250 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 4892937500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 10097469500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000461 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000569 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.009970 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.022455 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000643 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.011146 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.023607 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.013388 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.988183 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.990566 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.989385 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.383799 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.477609 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.432582 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000461 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000569 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.009970 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.148150 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000643 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011146 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.192187 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.062127 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000461 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000569 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.009970 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.148150 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000643 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011146 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.192187 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.062127 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 74583.333333 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 70500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 67221.929282 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 70268.112784 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 70000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 67488.164738 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 70544.877827 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 68590.245697 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17807.427504 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17821.146520 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17814.355531 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 67500 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 67500 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 64219.555845 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 63447.661929 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 63776.377369 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 74583.333333 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 70500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 67221.929282 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 64817.438245 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 70000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 67488.164738 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 63995.741504 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 64693.110291 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 74583.333333 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 70500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 67221.929282 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 64817.438245 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 70000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 67488.164738 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 63995.741504 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 64693.110291 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.membus.trans_dist::ReadReq 70492 # Transaction distribution +system.membus.trans_dist::ReadResp 70492 # Transaction distribution +system.membus.trans_dist::WriteReq 27594 # Transaction distribution +system.membus.trans_dist::WriteResp 27594 # Transaction distribution +system.membus.trans_dist::Writeback 116167 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4489 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4491 # Transaction distribution +system.membus.trans_dist::ReadExReq 126147 # Transaction distribution +system.membus.trans_dist::ReadExResp 126147 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2122 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 429068 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 536678 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108887 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 108887 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 645565 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4244 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 15156092 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 15319481 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 19954937 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 498 # Total snoops (count) +system.membus.snoop_fanout::samples 313389 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 313389 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 313389 # Request fanout histogram +system.membus.reqLayer0.occupancy 90494500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks) +system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer2.occupancy 1721500 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer5.occupancy 960656101 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.membus.respLayer2.occupancy 947025657 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.0 # Layer utilization (%) +system.membus.respLayer3.occupancy 37465995 # Layer occupancy (ticks) +system.membus.respLayer3.utilization 0.0 # Layer utilization (%) +system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU +system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post +system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR +system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post +system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post +system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR +system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post +system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post +system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR +system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post +system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post +system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post +system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post +system.realview.ethernet.postedInterrupts 0 # number of posts to CPU +system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.toL2Bus.trans_dist::ReadReq 2303937 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2303837 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 27594 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 27594 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 687030 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 36246 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2732 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2734 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 295743 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 295743 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3421816 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2454612 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 18880 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 35749 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5931057 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 108955768 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96785921 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 27096 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 50916 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 205819701 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 52269 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 3285526 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 3.011103 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.104785 # Request fanout histogram +system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 3249046 98.89% 98.89% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 36480 1.11% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 3285526 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 2359229000 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.snoopLayer0.occupancy 201000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 2567253247 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 1309775845 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 12106000 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 23020250 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/system.terminal b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/system.terminal new file mode 100644 index 000000000..b3be0ec54 --- /dev/null +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/system.terminal @@ -0,0 +1,208 @@ +Booting Linux on physical CPU 0x0 + Initializing cgroup subsys cpuset + Linux version 3.13.0-rc2 (tony@vamp) (gcc version 4.8.2 (Ubuntu/Linaro 4.8.2-16ubuntu4) ) #1 SMP PREEMPT Mon Oct 13 15:09:23 EDT 2014 + Kernel was built at commit id '' + CPU: ARMv7 Processor [410fc0f0] revision 0 (ARMv7), cr=10c53c7d + CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache + Machine model: V2P-CA15 + bootconsole [earlycon0] enabled + Memory policy: Data cache writealloc + kdebugv2m: Following are test values to confirm proper working + kdebugv2m: Ranges 42000000 0 + kdebugv2m: Regs 30000000 1000000 + kdebugv2m: Virtual-Reg f0000000 + kdebugv2m: pci node addr_cells 3 + kdebugv2m: pci node size_cells 2 + kdebugv2m: motherboard addr_cells 2 + On node 0 totalpages: 65536 + free_area_init_node: node 0, pgdat 8072dcc0, node_mem_map 8078f000 + Normal zone: 512 pages used for memmap + Normal zone: 0 pages reserved + Normal zone: 65536 pages, LIFO batch:15 + sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 178956969942ns + PERCPU: Embedded 8 pages/cpu @80996000 s11648 r8192 d12928 u32768 + pcpu-alloc: s11648 r8192 d12928 u32768 alloc=8*4096 + pcpu-alloc: [0] 0 + Built 1 zonelists in Zone order, mobility grouping on. Total pages: 65024 + Kernel command line: earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 + PID hash table entries: 1024 (order: 0, 4096 bytes) + Dentry cache hash table entries: 32768 (order: 5, 131072 bytes) + Inode-cache hash table entries: 16384 (order: 4, 65536 bytes) + Memory: 235688K/262144K available (5248K kernel code, 249K rwdata, 1540K rodata, 295K init, 368K bss, 26456K reserved, 0K highmem) + Virtual kernel memory layout: + vector : 0xffff0000 - 0xffff1000 ( 4 kB) + fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB) + vmalloc : 0x90800000 - 0xff000000 (1768 MB) + lowmem : 0x80000000 - 0x90000000 ( 256 MB) + pkmap : 0x7fe00000 - 0x80000000 ( 2 MB) + modules : 0x7f000000 - 0x7fe00000 ( 14 MB) + .text : 0x80008000 - 0x806a942c (6790 kB) + .init : 0x806aa000 - 0x806f3d80 ( 296 kB) + .data : 0x806f4000 - 0x80732754 ( 250 kB) + .bss : 0x80732754 - 0x8078e9d8 ( 369 kB) + SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1 + Preemptible hierarchical RCU implementation. + RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=1. + NR_IRQS:16 nr_irqs:16 16 + Architected cp15 timer(s) running at 25.16MHz (phys). + sched_clock: 56 bits at 25MHz, resolution 39ns, wraps every 2730666655744ns + Switching to timer-based delay loop + Console: colour dummy device 80x30 + Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480) + pid_max: default: 32768 minimum: 301 + Mount-cache hash table entries: 512 + CPU: Testing write buffer coherency: ok + CPU0: update cpu_power 1024 + CPU0: thread -1, cpu 0, socket 0, mpidr 80000000 + Setting up static identity map for 0x804fee68 - 0x804fee9c + Brought up 1 CPUs + SMP: Total of 1 processors activated. + CPU: All CPU(s) started in SVC mode. + VFP support v0.3: implementor 41 architecture 4 part 30 variant a rev 0 + NET: Registered protocol family 16 + DMA: preallocated 256 KiB pool for atomic coherent allocations + of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000 + of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/aaci@040000 + of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/mmci@050000 + of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000 + of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000 + of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000 + of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000 + hw-breakpoint: Debug register access (0xee113e93) caused undefined instruction on CPU 0 + hw-breakpoint: Debug register access (0xee013e90) caused undefined instruction on CPU 0 + hw-breakpoint: Debug register access (0xee003e17) caused undefined instruction on CPU 0 + hw-breakpoint: CPU 0 failed to disable vector catch + Serial: AMBA PL011 UART driver + 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3 + console [ttyAMA0] enabled +console [ttyAMA0] enabled + bootconsole [earlycon0] disabled +bootconsole [earlycon0] disabled + PCI host bridge to bus 0000:00 +pci_bus 0000:00: root bus resource [io 0x0000-0xffffffff] +pci_bus 0000:00: root bus resource [mem 0x00000000-0xffffffff] +pci_bus 0000:00: root bus resource [bus 00-ff] +pci 0000:00:00.0: [8086:1075] type 00 class 0x020000 +pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff] +pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref] +pci 0000:00:01.0: [8086:7111] type 00 class 0x010185 +pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007] +pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003] +pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007] +pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003] +pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f] +pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref] +PCI: bus0: Fast back to back transfers disabled +pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff] +pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref] +pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref] +pci 0000:00:01.0: BAR 4: assigned [io 0x2f000000-0x2f00000f] +pci 0000:00:01.0: BAR 0: assigned [io 0x2f000010-0x2f000017] +pci 0000:00:01.0: BAR 2: assigned [io 0x2f000018-0x2f00001f] +pci 0000:00:01.0: BAR 1: assigned [io 0x2f000020-0x2f000023] +pci 0000:00:01.0: BAR 3: assigned [io 0x2f000024-0x2f000027] +pci_bus 0000:00: resource 4 [io 0x0000-0xffffffff] +pci_bus 0000:00: resource 5 [mem 0x00000000-0xffffffff] +PCI map irq: slot 0, pin 1, devslot 0, irq: 68 +PCI map irq: slot 1, pin 2, devslot 1, irq: 69 +bio: create slab at 0 +vgaarb: loaded +SCSI subsystem initialized +libata version 3.00 loaded. +usbcore: registered new interface driver usbfs +usbcore: registered new interface driver hub +usbcore: registered new device driver usb +pps_core: LinuxPPS API ver. 1 registered +pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti +PTP clock support registered +Advanced Linux Sound Architecture Driver Initialized. +Switched to clocksource arch_sys_counter +NET: Registered protocol family 2 +TCP established hash table entries: 2048 (order: 1, 8192 bytes) +TCP bind hash table entries: 2048 (order: 2, 16384 bytes) +TCP: Hash tables configured (established 2048 bind 2048) +TCP: reno registered +UDP hash table entries: 256 (order: 1, 8192 bytes) +UDP-Lite hash table entries: 256 (order: 1, 8192 bytes) +NET: Registered protocol family 1 +RPC: Registered named UNIX socket transport module. +RPC: Registered udp transport module. +RPC: Registered tcp transport module. +RPC: Registered tcp NFSv4.1 backchannel transport module. +PCI: CLS 64 bytes, default 64 +hw perfevents: enabled with ARMv7_Cortex_A15 PMU driver, 1 counters available +jffs2: version 2.2. (NAND) © 2001-2006 Red Hat, Inc. +msgmni has been set to 460 +io scheduler noop registered (default) +brd: module loaded +loop: module loaded +ata_piix 0000:00:01.0: version 2.13 +PCI: enabling device 0000:00:01.0 (0040 -> 0041) +scsi0 : ata_piix +scsi1 : ata_piix +ata1: PATA max UDMA/33 cmd 0x2f000010 ctl 0x2f000020 bmdma 0x2f000000 irq 69 +ata2: PATA max UDMA/33 cmd 0x2f000018 ctl 0x2f000024 bmdma 0x2f000008 irq 69 +e100: Intel(R) PRO/100 Network Driver, 3.5.24-k2-NAPI +e100: Copyright(c) 1999-2006 Intel Corporation +e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI +e1000: Copyright (c) 1999-2006 Intel Corporation. +PCI: enabling device 0000:00:00.0 (0040 -> 0042) +ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66 +ata1.00: 1048320 sectors, multi 0: LBA +ata1.00: configured for UDMA/33 +scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5 +sd 0:0:0:0: [sda] 1048320 512-byte logical blocks: (536 MB/511 MiB) +sd 0:0:0:0: [sda] Write Protect is off +sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00 +sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA + sda: sda1 +sd 0:0:0:0: Attached scsi generic sg0 type 0 +sd 0:0:0:0: [sda] Attached SCSI disk +e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01 +e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection +e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k +e1000e: Copyright(c) 1999 - 2013 Intel Corporation. +igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k +igb: Copyright (c) 2007-2013 Intel Corporation. +igbvf: Intel(R) Gigabit Virtual Function Network Driver - version 2.0.2-k +igbvf: Copyright (c) 2009 - 2012 Intel Corporation. +ixgbe: Intel(R) 10 Gigabit PCI Express Network Driver - version 3.15.1-k +ixgbe: Copyright (c) 1999-2013 Intel Corporation. +ixgbevf: Intel(R) 10 Gigabit PCI Express Virtual Function Network Driver - version 2.11.3-k +ixgbevf: Copyright (c) 2009 - 2012 Intel Corporation. +ixgb: Intel(R) PRO/10GbE Network Driver - version 1.0.135-k2-NAPI +ixgb: Copyright (c) 1999-2008 Intel Corporation. +smsc911x: Driver version 2008-10-21 +smsc911x 1a000000.ethernet (unregistered net_device): couldn't get clock -2 +nxp-isp1760 1b000000.usb: NXP ISP1760 USB Host Controller +nxp-isp1760 1b000000.usb: new USB bus registered, assigned bus number 1 +nxp-isp1760 1b000000.usb: Scratch test failed. +nxp-isp1760 1b000000.usb: can't setup: -19 +nxp-isp1760 1b000000.usb: USB bus 1 deregistered +usbcore: registered new interface driver usb-storage +mousedev: PS/2 mouse device common for all mice +rtc-pl031 1c170000.rtc: rtc core: registered pl031 as rtc0 +usbcore: registered new interface driver usbhid +usbhid: USB HID core driver +ashmem: initialized +logger: created 256K log 'log_main' +logger: created 256K log 'log_events' +logger: created 256K log 'log_radio' +logger: created 256K log 'log_system' +oprofile: using timer interrupt. +TCP: cubic registered +NET: Registered protocol family 10 +NET: Registered protocol family 17 +rtc-pl031 1c170000.rtc: setting system clock to 2009-01-01 12:00:00 UTC (1230811200) +ALSA device list: + No soundcards found. +input: AT Raw Set 2 keyboard as /devices/smb.14/motherboard.15/iofpga.17/1c060000.kmi/serio0/input/input0 +input: touchkitPS/2 eGalax Touchscreen as /devices/smb.14/motherboard.15/iofpga.17/1c070000.kmi/serio1/input/input2 +VFS: Mounted root (ext2 filesystem) on device 8:1. +Freeing unused kernel memory: 292K (806aa000 - 806f3000) + init started: BusyBox v1.15.3 (2010-05-07 01:27:07 BST) + starting pid 673, tty '': '/etc/rc.d/rc.local' +warning: can't open /etc/mtab: No such file or directory +Thu Jan 1 12:00:02 UTC 2009 +S: devpts +Thu Jan 1 12:00:02 UTC 2009 diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/chair.cook.ppm b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/chair.cook.ppm new file mode 100644 index 000000000..9ac19076f --- /dev/null +++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/chair.cook.ppm @@ -0,0 +1,4 @@ +P6 +15 15 +255 +   !!!  !!!$$$&&&'''&&&%%% !!!%%%(((******)))(((!!!###'''***+++,,,+++)))"""###''')))++++++***)))!!!!!!%%%((()))))))))''' """%%%&&&'''&&&%%%%%%  !!!"""#########"""(((---222666&&&...///===;;;999555111,,,((($$$DDDKKKRRRXXXBBB†††‘‘‘jjjWWWZZZUUUNNNGGG???888[[[dddkkkrrr]]]CCC===eeeaaarrrkkkddd[[[SSSKKKiiipppvvvvvvEEEggg{{{uuunnnfff^^^VVVmmmsssxxx|||oooEEEDDD]]]vvvzzzuuuooohhhaaaZZZjjjooossswwwyyyzzzzzzyyywwwtttoookkkeee```ZZZeeeiiilllnnnpppppppppooonnnkkkhhhddd```\\\WWW \ No newline at end of file diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/config.ini b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/config.ini new file mode 100644 index 000000000..392920ac8 --- /dev/null +++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/config.ini @@ -0,0 +1,270 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +eventq_index=0 +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=atomic +mem_ranges= +memories=system.physmem +num_work_ids=16 +readfile= +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=AtomicSimpleCPU +children=dstage2_mmu dtb interrupts isa istage2_mmu itb tracer workload +branchPred=Null +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu +dtb=system.cpu.dtb +eventq_index=0 +fastmem=false +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +istage2_mmu=system.cpu.istage2_mmu +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +profile=0 +progress_interval=0 +simpoint_start_insts= +simulate_data_stalls=false +simulate_inst_stalls=false +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +width=1 +workload=system.cpu.workload +dcache_port=system.membus.slave[2] +icache_port=system.membus.slave[1] + +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.membus.slave[6] + +[system.cpu.dtb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system +port=system.membus.slave[4] + +[system.cpu.interrupts] +type=ArmInterrupts +eventq_index=0 + +[system.cpu.isa] +type=ArmISA +eventq_index=0 +fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=270536963 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=34611729 +id_pfr0=49 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.membus.slave[5] + +[system.cpu.itb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system +port=system.membus.slave[3] + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=mcf mcf.in +cwd=build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/mcf +gid=100 +input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=55300000000 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.membus] +type=CoherentXBar +clk_domain=system.clk_domain +eventq_index=0 +header_cycles=1 +snoop_filter=Null +system=system +use_default_range=false +width=8 +master=system.physmem.port +slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port + +[system.physmem] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=true +eventq_index=0 +in_addr_map=true +latency=30000 +latency_var=0 +null=false +range=0:268435455 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/mcf.out b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/mcf.out new file mode 100644 index 000000000..095132477 --- /dev/null +++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/mcf.out @@ -0,0 +1,999 @@ +() +500 +() +499 +() +498 +() +496 +() +495 +() +494 +() +493 +() +492 +() +491 +() +490 +() +489 +() +488 +() +487 +() +486 +() +484 +() +482 +() +481 +() +480 +() +479 +() +478 +() +477 +() +476 +() +475 +() +474 +() +473 +() +472 +() +471 +() +469 +() +468 +() +467 +() +466 +() +465 +() +464 +() +463 +() +462 +() +461 +() +460 +() +459 +() +458 +() +457 +() +455 +() +454 +() +452 +() +451 +() +450 +() +449 +() +448 +() +446 +() +445 +() +444 +() +443 +() +442 +() +440 +() +439 +() +438 +() +436 +() +435 +() +433 +() +432 +() +431 +() +428 +() +427 +() +425 +() +424 +() +423 +() +420 +() +419 +() +416 +() +414 +() +413 +() +412 +() +407 +() +406 +() +405 +() +404 +() +403 +() +402 +() +401 +() +400 +() +399 +() +398 +() +396 +() +395 +() +393 +() +392 +() +390 +() +389 +() +388 +() +387 +() +386 +() +385 +() +384 +() +383 +() +382 +() +381 +() +380 +() +379 +() +377 +() +375 +() +374 +() +373 +() +372 +() +371 +() +370 +() +369 +() +368 +() +366 +() +365 +() +364 +() +362 +() +361 +() +360 +() +359 +() +358 +() +357 +() +356 +() +355 +() +354 +() +352 +() +350 +() +347 +() +344 +() +342 +() +341 +() +340 +() +339 +() +338 +() +332 +() +325 +() +320 +*** +345 +() +319 +*** +497 +() +318 +*** +349 +() +317 +*** +408 +() +316 +*** +324 +() +315 +*** +328 +() +314 +*** +335 +() +313 +*** +378 +() +312 +*** +426 +() +311 +*** +411 +() +304 +*** +343 +() +303 +*** +417 +() +302 +*** +485 +() +301 +*** +363 +() +300 +*** +376 +() +299 +*** +333 +() +292 +*** +337 +() +291 +*** +409 +() +290 +*** +421 +() +289 +*** +437 +() +288 +*** +430 +() +287 +*** +348 +() +286 +*** +326 +() +284 +() +282 +*** +308 +() +279 +*** +297 +*** +305 +() +278 +() +277 +*** +307 +() +276 +*** +296 +() +273 +() +271 +() +265 +() +246 +*** +267 +() +245 +*** +280 +() +244 +*** +391 +() +243 +*** +330 +() +242 +*** +456 +() +241 +*** +346 +() +240 +*** +483 +() +239 +*** +260 +() +238 +*** +261 +() +237 +*** +262 +*** +294 +() +236 +*** +253 +() +229 +*** +397 +() +228 +*** +298 +() +227 +*** +415 +() +226 +*** +264 +() +224 +*** +232 +() +222 +*** +233 +() +217 +*** +250 +() +211 +*** +331 +() +210 +*** +394 +() +209 +*** +410 +() +208 +*** +321 +() +207 +*** +327 +() +206 +*** +309 +() +199 +*** +259 +() +198 +*** +219 +() +197 +*** +220 +() +195 +*** +429 +() +194 +*** +470 +() +193 +*** +274 +() +191 +*** +203 +() +190 +*** +263 +() +189 +215 +*** +230 +() +188 +*** +266 +*** +295 +() +182 +*** +329 +() +181 +*** +351 +() +180 +*** +441 +() +179 +*** +453 +() +178 +*** +418 +() +177 +*** +353 +() +176 +*** +422 +() +175 +*** +225 +*** +255 +() +174 +*** +269 +() +173 +*** +214 +() +172 +*** +186 +() +171 +*** +447 +() +170 +*** +270 +*** +306 +() +169 +*** +336 +() +168 +*** +285 +() +165 +*** +249 +() +146 +*** +154 +() +143 +*** +334 +() +142 +*** +216 +*** +257 +() +141 +*** +167 +*** +251 +() +140 +*** +162 +*** +293 +() +139 +*** +158 +() +137 +*** +166 +*** +201 +() +136 +*** +160 +() +134 +*** +221 +() +132 +*** +213 +() +131 +*** +187 +() +129 +*** +235 +() +128 +*** +153 +() +127 +*** +156 +() +126 +*** +159 +*** +218 +() +125 +*** +155 +() +124 +*** +157 +() +123 +*** +152 +() +116 +*** +135 +*** +163 +() +115 +*** +133 +*** +204 +*** +248 +() +114 +*** +192 +*** +212 +() +113 +*** +268 +() +112 +*** +367 +() +111 +*** +272 +() +110 +*** +434 +() +109 +*** +323 +() +108 +*** +281 +() +107 +*** +144 +*** +148 +() +106 +*** +275 +() +105 +*** +196 +*** +254 +() +104 +*** +138 +*** +161 +() +103 +*** +310 +() +102 +*** +223 +*** +252 +() +80 +() +70 +() +69 +() +68 +() +66 +() +64 +() +62 +*** +256 +() +61 +*** +93 +() +59 +*** +120 +() +58 +() +57 +*** +183 +() +55 +() +54 +() +52 +*** +147 +() +51 +*** +118 +() +50 +*** +83 +() +49 +*** +98 +() +48 +*** +99 +() +47 +() +46 +*** +184 +() +45 +*** +121 +() +44 +() +43 +*** +88 +() +42 +*** +122 +() +41 +*** +91 +() +40 +*** +96 +() +38 +*** +100 +() +37 +*** +149 +() +36 +*** +74 +() +35 +*** +258 +() +34 +*** +151 +() +33 +*** +85 +() +32 +() +31 +*** +94 +() +30 +*** +97 +() +29 +*** +90 +() +28 +*** +89 +() +27 +*** +92 +() +26 +*** +72 +*** +247 +() +25 +*** +86 +() +24 +*** +82 +() +23 +*** +87 +*** +117 +() +22 +*** +76 +*** +119 +() +21 +*** +84 +() +20 +*** +78 +() +19 +*** +73 +() +18 +*** +81 +() +17 +*** +65 +() +16 +*** +63 +*** +101 +() +15 +*** +71 +() +14 +*** +75 +() +13 +*** +322 +() +12 +*** +77 +() +11 +*** +283 +() +10 +*** +79 +() +9 +*** +145 +*** +150 +() +8 +*** +67 +() +7 +*** +60 +*** +231 +() +6 +*** +56 +*** +234 +() +5 +*** +164 +*** +202 +() +4 +*** +53 +() +3 +*** +130 +*** +185 +*** +200 +() +2 +*** +205 +() +1 +*** +39 +*** +95 diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/simerr b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/simerr new file mode 100755 index 000000000..1a4f96712 --- /dev/null +++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/simerr @@ -0,0 +1 @@ +warn: Sockets disabled, not accepting gdb connections diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/simout b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/simout new file mode 100755 index 000000000..c759bbe65 --- /dev/null +++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/simout @@ -0,0 +1,27 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Jan 23 2014 12:08:08 +gem5 started Jan 23 2014 17:11:38 +gem5 executing on u200540-lin +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic +Global frequency set at 1000000000000 ticks per second + 0: system.cpu.isa: ISA system set to: 0 0x63b66c0 +info: Entering event queue @ 0. Starting simulation... + +MCF SPEC version 1.6.I +by Andreas Loebel +Copyright (c) 1998,1999 ZIB Berlin +All Rights Reserved. + +nodes : 500 +active arcs : 1905 +simplex iterations : 1502 +flow value : 4990014995 +new implicit arcs : 23867 +active arcs : 25772 +simplex iterations : 2663 +flow value : 3080014995 +checksum : 68389 +optimal +Exiting @ tick 54240661000 because target called exit() diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt new file mode 100644 index 000000000..b143a6790 --- /dev/null +++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt @@ -0,0 +1,245 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.054141 # Number of seconds simulated +sim_ticks 54141000000 # Number of ticks simulated +final_tick 54141000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 1893120 # Simulator instruction rate (inst/s) +host_op_rate 1902548 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1131265211 # Simulator tick rate (ticks/s) +host_mem_usage 433636 # Number of bytes of host memory used +host_seconds 47.86 # Real time elapsed on the host +sim_insts 90602407 # Number of instructions simulated +sim_ops 91053638 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 431323080 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 90016598 # Number of bytes read from this memory +system.physmem.bytes_read::total 521339678 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 431323080 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 431323080 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 18908138 # Number of bytes written to this memory +system.physmem.bytes_written::total 18908138 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 107830770 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 22461532 # Number of read requests responded to by this memory +system.physmem.num_reads::total 130292302 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 4738868 # Number of write requests responded to by this memory +system.physmem.num_writes::total 4738868 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 7966662603 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1662632718 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 9629295321 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7966662603 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7966662603 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 349238802 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 349238802 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7966662603 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2011871521 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 9978534124 # Total bandwidth to/from this memory (bytes/s) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 442 # Number of system calls +system.cpu.numCycles 108282001 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 90602407 # Number of instructions committed +system.cpu.committedOps 91053638 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 72326352 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses +system.cpu.num_func_calls 112245 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 15520157 # number of instructions that are conditional controls +system.cpu.num_int_insts 72326352 # number of integer instructions +system.cpu.num_fp_insts 48 # number of float instructions +system.cpu.num_int_register_reads 124257699 # number of times the integer registers were read +system.cpu.num_int_register_writes 52782988 # number of times the integer registers were written +system.cpu.num_fp_register_reads 54 # number of times the floating registers were read +system.cpu.num_fp_register_writes 30 # number of times the floating registers were written +system.cpu.num_cc_register_reads 271814240 # number of times the CC registers were read +system.cpu.num_cc_register_writes 53956115 # number of times the CC registers were written +system.cpu.num_mem_refs 27220755 # number of memory refs +system.cpu.num_load_insts 22475911 # Number of load instructions +system.cpu.num_store_insts 4744844 # Number of store instructions +system.cpu.num_idle_cycles 0.002000 # Number of idle cycles +system.cpu.num_busy_cycles 108282000.998000 # Number of busy cycles +system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.000000 # Percentage of idle cycles +system.cpu.Branches 18732304 # Number of branches fetched +system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction +system.cpu.op_class::IntAlu 63822828 70.09% 70.09% # Class of executed instruction +system.cpu.op_class::IntMult 10474 0.01% 70.10% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 6 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 15 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 2 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::MemRead 22475911 24.68% 94.79% # Class of executed instruction +system.cpu.op_class::MemWrite 4744844 5.21% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 91054080 # Class of executed instruction +system.membus.trans_dist::ReadReq 130287905 # Transaction distribution +system.membus.trans_dist::ReadResp 130291792 # Transaction distribution +system.membus.trans_dist::WriteReq 4734981 # Transaction distribution +system.membus.trans_dist::WriteResp 4734981 # Transaction distribution +system.membus.trans_dist::SoftPFReq 510 # Transaction distribution +system.membus.trans_dist::SoftPFResp 510 # Transaction distribution +system.membus.trans_dist::LoadLockedReq 3887 # Transaction distribution +system.membus.trans_dist::StoreCondReq 3887 # Transaction distribution +system.membus.trans_dist::StoreCondResp 3887 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 215661540 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 54400800 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 270062340 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 431323080 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 108924736 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 540247816 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 135031170 # Request fanout histogram +system.membus.snoop_fanout::mean 2.798562 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.401074 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::2 27200400 20.14% 20.14% # Request fanout histogram +system.membus.snoop_fanout::3 107830770 79.86% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 2 # Request fanout histogram +system.membus.snoop_fanout::max_value 3 # Request fanout histogram +system.membus.snoop_fanout::total 135031170 # Request fanout histogram + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/chair.cook.ppm b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/chair.cook.ppm new file mode 100644 index 000000000..9ac19076f --- /dev/null +++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/chair.cook.ppm @@ -0,0 +1,4 @@ +P6 +15 15 +255 +   !!!  !!!$$$&&&'''&&&%%% !!!%%%(((******)))(((!!!###'''***+++,,,+++)))"""###''')))++++++***)))!!!!!!%%%((()))))))))''' """%%%&&&'''&&&%%%%%%  !!!"""#########"""(((---222666&&&...///===;;;999555111,,,((($$$DDDKKKRRRXXXBBB†††‘‘‘jjjWWWZZZUUUNNNGGG???888[[[dddkkkrrr]]]CCC===eeeaaarrrkkkddd[[[SSSKKKiiipppvvvvvvEEEggg{{{uuunnnfff^^^VVVmmmsssxxx|||oooEEEDDD]]]vvvzzzuuuooohhhaaaZZZjjjooossswwwyyyzzzzzzyyywwwtttoookkkeee```ZZZeeeiiilllnnnpppppppppooonnnkkkhhhddd```\\\WWW \ No newline at end of file diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/config.ini b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/config.ini new file mode 100644 index 000000000..e662df1f5 --- /dev/null +++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/config.ini @@ -0,0 +1,383 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +eventq_index=0 +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges= +memories=system.physmem +num_work_ids=16 +readfile= +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=TimingSimpleCPU +children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload +branchPred=Null +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu +dtb=system.cpu.dtb +eventq_index=0 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +istage2_mmu=system.cpu.istage2_mmu +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=262144 +system=system +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=262144 + +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[5] + +[system.cpu.dtb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[3] + +[system.cpu.icache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=131072 +system=system +tags=system.cpu.icache.tags +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.slave[0] + +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=131072 + +[system.cpu.interrupts] +type=ArmInterrupts +eventq_index=0 + +[system.cpu.isa] +type=ArmISA +eventq_index=0 +fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=270536963 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=34611729 +id_pfr0=49 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[4] + +[system.cpu.itb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[2] + +[system.cpu.l2cache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=20 +is_top_level=false +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=2097152 +system=system +tags=system.cpu.l2cache.tags +tgts_per_mshr=12 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] + +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=20 +sequential_access=false +size=2097152 + +[system.cpu.toL2Bus] +type=CoherentXBar +clk_domain=system.cpu_clk_domain +eventq_index=0 +header_cycles=1 +snoop_filter=Null +system=system +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=mcf mcf.in +cwd=build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-timing +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/mcf +gid=100 +input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=55300000000 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.membus] +type=CoherentXBar +clk_domain=system.clk_domain +eventq_index=0 +header_cycles=1 +snoop_filter=Null +system=system +use_default_range=false +width=8 +master=system.physmem.port +slave=system.system_port system.cpu.l2cache.mem_side + +[system.physmem] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=true +eventq_index=0 +in_addr_map=true +latency=30000 +latency_var=0 +null=false +range=0:268435455 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/mcf.out b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/mcf.out new file mode 100644 index 000000000..095132477 --- /dev/null +++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/mcf.out @@ -0,0 +1,999 @@ +() +500 +() +499 +() +498 +() +496 +() +495 +() +494 +() +493 +() +492 +() +491 +() +490 +() +489 +() +488 +() +487 +() +486 +() +484 +() +482 +() +481 +() +480 +() +479 +() +478 +() +477 +() +476 +() +475 +() +474 +() +473 +() +472 +() +471 +() +469 +() +468 +() +467 +() +466 +() +465 +() +464 +() +463 +() +462 +() +461 +() +460 +() +459 +() +458 +() +457 +() +455 +() +454 +() +452 +() +451 +() +450 +() +449 +() +448 +() +446 +() +445 +() +444 +() +443 +() +442 +() +440 +() +439 +() +438 +() +436 +() +435 +() +433 +() +432 +() +431 +() +428 +() +427 +() +425 +() +424 +() +423 +() +420 +() +419 +() +416 +() +414 +() +413 +() +412 +() +407 +() +406 +() +405 +() +404 +() +403 +() +402 +() +401 +() +400 +() +399 +() +398 +() +396 +() +395 +() +393 +() +392 +() +390 +() +389 +() +388 +() +387 +() +386 +() +385 +() +384 +() +383 +() +382 +() +381 +() +380 +() +379 +() +377 +() +375 +() +374 +() +373 +() +372 +() +371 +() +370 +() +369 +() +368 +() +366 +() +365 +() +364 +() +362 +() +361 +() +360 +() +359 +() +358 +() +357 +() +356 +() +355 +() +354 +() +352 +() +350 +() +347 +() +344 +() +342 +() +341 +() +340 +() +339 +() +338 +() +332 +() +325 +() +320 +*** +345 +() +319 +*** +497 +() +318 +*** +349 +() +317 +*** +408 +() +316 +*** +324 +() +315 +*** +328 +() +314 +*** +335 +() +313 +*** +378 +() +312 +*** +426 +() +311 +*** +411 +() +304 +*** +343 +() +303 +*** +417 +() +302 +*** +485 +() +301 +*** +363 +() +300 +*** +376 +() +299 +*** +333 +() +292 +*** +337 +() +291 +*** +409 +() +290 +*** +421 +() +289 +*** +437 +() +288 +*** +430 +() +287 +*** +348 +() +286 +*** +326 +() +284 +() +282 +*** +308 +() +279 +*** +297 +*** +305 +() +278 +() +277 +*** +307 +() +276 +*** +296 +() +273 +() +271 +() +265 +() +246 +*** +267 +() +245 +*** +280 +() +244 +*** +391 +() +243 +*** +330 +() +242 +*** +456 +() +241 +*** +346 +() +240 +*** +483 +() +239 +*** +260 +() +238 +*** +261 +() +237 +*** +262 +*** +294 +() +236 +*** +253 +() +229 +*** +397 +() +228 +*** +298 +() +227 +*** +415 +() +226 +*** +264 +() +224 +*** +232 +() +222 +*** +233 +() +217 +*** +250 +() +211 +*** +331 +() +210 +*** +394 +() +209 +*** +410 +() +208 +*** +321 +() +207 +*** +327 +() +206 +*** +309 +() +199 +*** +259 +() +198 +*** +219 +() +197 +*** +220 +() +195 +*** +429 +() +194 +*** +470 +() +193 +*** +274 +() +191 +*** +203 +() +190 +*** +263 +() +189 +215 +*** +230 +() +188 +*** +266 +*** +295 +() +182 +*** +329 +() +181 +*** +351 +() +180 +*** +441 +() +179 +*** +453 +() +178 +*** +418 +() +177 +*** +353 +() +176 +*** +422 +() +175 +*** +225 +*** +255 +() +174 +*** +269 +() +173 +*** +214 +() +172 +*** +186 +() +171 +*** +447 +() +170 +*** +270 +*** +306 +() +169 +*** +336 +() +168 +*** +285 +() +165 +*** +249 +() +146 +*** +154 +() +143 +*** +334 +() +142 +*** +216 +*** +257 +() +141 +*** +167 +*** +251 +() +140 +*** +162 +*** +293 +() +139 +*** +158 +() +137 +*** +166 +*** +201 +() +136 +*** +160 +() +134 +*** +221 +() +132 +*** +213 +() +131 +*** +187 +() +129 +*** +235 +() +128 +*** +153 +() +127 +*** +156 +() +126 +*** +159 +*** +218 +() +125 +*** +155 +() +124 +*** +157 +() +123 +*** +152 +() +116 +*** +135 +*** +163 +() +115 +*** +133 +*** +204 +*** +248 +() +114 +*** +192 +*** +212 +() +113 +*** +268 +() +112 +*** +367 +() +111 +*** +272 +() +110 +*** +434 +() +109 +*** +323 +() +108 +*** +281 +() +107 +*** +144 +*** +148 +() +106 +*** +275 +() +105 +*** +196 +*** +254 +() +104 +*** +138 +*** +161 +() +103 +*** +310 +() +102 +*** +223 +*** +252 +() +80 +() +70 +() +69 +() +68 +() +66 +() +64 +() +62 +*** +256 +() +61 +*** +93 +() +59 +*** +120 +() +58 +() +57 +*** +183 +() +55 +() +54 +() +52 +*** +147 +() +51 +*** +118 +() +50 +*** +83 +() +49 +*** +98 +() +48 +*** +99 +() +47 +() +46 +*** +184 +() +45 +*** +121 +() +44 +() +43 +*** +88 +() +42 +*** +122 +() +41 +*** +91 +() +40 +*** +96 +() +38 +*** +100 +() +37 +*** +149 +() +36 +*** +74 +() +35 +*** +258 +() +34 +*** +151 +() +33 +*** +85 +() +32 +() +31 +*** +94 +() +30 +*** +97 +() +29 +*** +90 +() +28 +*** +89 +() +27 +*** +92 +() +26 +*** +72 +*** +247 +() +25 +*** +86 +() +24 +*** +82 +() +23 +*** +87 +*** +117 +() +22 +*** +76 +*** +119 +() +21 +*** +84 +() +20 +*** +78 +() +19 +*** +73 +() +18 +*** +81 +() +17 +*** +65 +() +16 +*** +63 +*** +101 +() +15 +*** +71 +() +14 +*** +75 +() +13 +*** +322 +() +12 +*** +77 +() +11 +*** +283 +() +10 +*** +79 +() +9 +*** +145 +*** +150 +() +8 +*** +67 +() +7 +*** +60 +*** +231 +() +6 +*** +56 +*** +234 +() +5 +*** +164 +*** +202 +() +4 +*** +53 +() +3 +*** +130 +*** +185 +*** +200 +() +2 +*** +205 +() +1 +*** +39 +*** +95 diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/simerr b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/simerr new file mode 100755 index 000000000..1a4f96712 --- /dev/null +++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/simerr @@ -0,0 +1 @@ +warn: Sockets disabled, not accepting gdb connections diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/simout b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/simout new file mode 100755 index 000000000..ea901fcca --- /dev/null +++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/simout @@ -0,0 +1,27 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Jan 23 2014 12:08:08 +gem5 started Jan 23 2014 17:12:31 +gem5 executing on u200540-lin +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-timing +Global frequency set at 1000000000000 ticks per second + 0: system.cpu.isa: ISA system set to: 0 0x5565040 +info: Entering event queue @ 0. Starting simulation... + +MCF SPEC version 1.6.I +by Andreas Loebel +Copyright (c) 1998,1999 ZIB Berlin +All Rights Reserved. + +nodes : 500 +active arcs : 1905 +simplex iterations : 1502 +flow value : 4990014995 +new implicit arcs : 23867 +active arcs : 25772 +simplex iterations : 2663 +flow value : 3080014995 +checksum : 68389 +optimal +Exiting @ tick 147135976000 because target called exit() diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt new file mode 100644 index 000000000..7176a8af9 --- /dev/null +++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt @@ -0,0 +1,634 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.147041 # Number of seconds simulated +sim_ticks 147041218500 # Number of ticks simulated +final_tick 147041218500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 937429 # Simulator instruction rate (inst/s) +host_op_rate 942087 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1521808702 # Simulator tick rate (ticks/s) +host_mem_usage 442868 # Number of bytes of host memory used +host_seconds 96.62 # Real time elapsed on the host +sim_insts 90576861 # Number of instructions simulated +sim_ops 91026990 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 36992 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 944768 # Number of bytes read from this memory +system.physmem.bytes_read::total 981760 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 36992 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 36992 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 578 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 14762 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15340 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 251576 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 6425192 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6676767 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 251576 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 251576 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 251576 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 6425192 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6676767 # Total bandwidth to/from this memory (bytes/s) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 442 # Number of system calls +system.cpu.numCycles 294082437 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 90576861 # Number of instructions committed +system.cpu.committedOps 91026990 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 72326352 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses +system.cpu.num_func_calls 112245 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 15520157 # number of instructions that are conditional controls +system.cpu.num_int_insts 72326352 # number of integer instructions +system.cpu.num_fp_insts 48 # number of float instructions +system.cpu.num_int_register_reads 124237033 # number of times the integer registers were read +system.cpu.num_int_register_writes 52782988 # number of times the integer registers were written +system.cpu.num_fp_register_reads 54 # number of times the floating registers were read +system.cpu.num_fp_register_writes 30 # number of times the floating registers were written +system.cpu.num_cc_register_reads 339191618 # number of times the CC registers were read +system.cpu.num_cc_register_writes 53956115 # number of times the CC registers were written +system.cpu.num_mem_refs 27220755 # number of memory refs +system.cpu.num_load_insts 22475911 # Number of load instructions +system.cpu.num_store_insts 4744844 # Number of store instructions +system.cpu.num_idle_cycles 0.002000 # Number of idle cycles +system.cpu.num_busy_cycles 294082436.998000 # Number of busy cycles +system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.000000 # Percentage of idle cycles +system.cpu.Branches 18732304 # Number of branches fetched +system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction +system.cpu.op_class::IntAlu 63822828 70.09% 70.09% # Class of executed instruction +system.cpu.op_class::IntMult 10474 0.01% 70.10% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 6 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 15 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 2 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::MemRead 22475911 24.68% 94.79% # Class of executed instruction +system.cpu.op_class::MemWrite 4744844 5.21% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 91054080 # Class of executed instruction +system.cpu.dcache.tags.replacements 942702 # number of replacements +system.cpu.dcache.tags.tagsinuse 3565.593939 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 26253601 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 946798 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 27.728830 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 54410414000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3565.593939 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.870506 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.870506 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 135 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1355 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2550 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 56 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 55347598 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 55347598 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 21556948 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21556948 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4688372 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4688372 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 507 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 507 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 26245320 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26245320 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26245827 # number of overall hits +system.cpu.dcache.overall_hits::total 26245827 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 900187 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 900187 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 46609 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 46609 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 3 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 3 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 946796 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 946796 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 946799 # number of overall misses +system.cpu.dcache.overall_misses::total 946799 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11711364000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11711364000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1217183500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1217183500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 12928547500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 12928547500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 12928547500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 12928547500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22457135 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22457135 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 510 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 510 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 27192116 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 27192116 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 27192626 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 27192626 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040085 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.040085 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009844 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.009844 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.005882 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.005882 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.034819 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.034819 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.034818 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.034818 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13009.923494 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13009.923494 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26114.773971 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 26114.773971 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 13655.050824 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 13655.050824 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 13655.007557 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 13655.007557 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 942334 # number of writebacks +system.cpu.dcache.writebacks::total 942334 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 900186 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 900186 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46609 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 46609 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 946795 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 946795 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 946798 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 946798 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10361045000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10361045000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1147270000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1147270000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 118500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 118500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11508315000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11508315000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11508433500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11508433500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040085 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040085 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009844 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009844 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.005882 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.005882 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034819 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.034819 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034818 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.034818 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11509.893511 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11509.893511 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24614.773971 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24614.773971 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 39500 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 39500 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12155.022999 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 12155.022999 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12155.109643 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 12155.109643 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.tags.replacements 2 # number of replacements +system.cpu.icache.tags.tagsinuse 510.120572 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 107830172 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 599 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 180016.981636 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.120572 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.249082 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.249082 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 597 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 552 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.291504 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 215662141 # Number of tag accesses +system.cpu.icache.tags.data_accesses 215662141 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 107830172 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 107830172 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 107830172 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 107830172 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 107830172 # number of overall hits +system.cpu.icache.overall_hits::total 107830172 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 599 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 599 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 599 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 599 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 599 # number of overall misses +system.cpu.icache.overall_misses::total 599 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 32074000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 32074000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 32074000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 32074000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 32074000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 32074000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 107830771 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 107830771 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 107830771 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 107830771 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 107830771 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 107830771 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000006 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000006 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000006 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000006 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000006 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000006 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53545.909850 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 53545.909850 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 53545.909850 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 53545.909850 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 53545.909850 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 53545.909850 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 599 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 599 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 599 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 599 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 599 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 599 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 31175500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 31175500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 31175500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 31175500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 31175500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 31175500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000006 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000006 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000006 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52045.909850 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52045.909850 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52045.909850 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 52045.909850 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52045.909850 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 52045.909850 # average overall mshr miss latency +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 9567.852421 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1827177 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 15323 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 119.244078 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 8879.446344 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 495.172977 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 193.233100 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.270979 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.015111 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.005897 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.291988 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 15323 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 105 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1468 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13704 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.467621 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 15179780 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 15179780 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 21 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 899975 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 899996 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 942334 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 942334 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 32061 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 32061 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 21 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 932036 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 932057 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 21 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 932036 # number of overall hits +system.cpu.l2cache.overall_hits::total 932057 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 578 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 214 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 792 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 14548 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 14548 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 578 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 14762 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 15340 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 578 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 14762 # number of overall misses +system.cpu.l2cache.overall_misses::total 15340 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 30356000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11237000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 41593000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 764020500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 764020500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 30356000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 775257500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 805613500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 30356000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 775257500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 805613500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 599 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 900189 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 900788 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 942334 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 942334 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 46609 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 46609 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 599 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 946798 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 947397 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 599 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 946798 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 947397 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.964942 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000238 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.000879 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.312129 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.312129 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.964942 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.015591 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.016192 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.964942 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.015591 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.016192 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52519.031142 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52509.345794 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52516.414141 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52517.218862 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52517.218862 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52519.031142 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52517.104728 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52517.177314 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52519.031142 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52517.104728 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52517.177314 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 578 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 214 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 792 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14548 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 14548 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 578 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 14762 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 15340 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 578 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 14762 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 15340 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 23409000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8667000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 32076000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 589194000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 589194000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23409000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 597861000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 621270000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23409000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 597861000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 621270000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.964942 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000238 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000879 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.312129 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.312129 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.964942 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015591 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.016192 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.964942 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015591 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.016192 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 900788 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 900788 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 942334 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 46609 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 46609 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1198 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2835930 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2837128 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 38336 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120904448 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 120942784 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 1889731 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 1889731 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 1889731 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 1887199500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 898500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 1420197000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) +system.membus.trans_dist::ReadReq 792 # Transaction distribution +system.membus.trans_dist::ReadResp 792 # Transaction distribution +system.membus.trans_dist::ReadExReq 14548 # Transaction distribution +system.membus.trans_dist::ReadExResp 14548 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 30680 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 30680 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 981760 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 981760 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 15340 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 15340 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 15340 # Request fanout histogram +system.membus.reqLayer0.occupancy 15603500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 76963500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.1 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini new file mode 100644 index 000000000..5a8877655 --- /dev/null +++ b/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini @@ -0,0 +1,171 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +eventq_index=0 +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=atomic +mem_ranges= +memories=system.physmem +num_work_ids=16 +readfile= +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=AtomicSimpleCPU +children=dtb interrupts isa itb tracer workload +branchPred=Null +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fastmem=false +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +profile=0 +progress_interval=0 +simpoint_start_insts= +simulate_data_stalls=false +simulate_inst_stalls=false +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +width=1 +workload=system.cpu.workload +dcache_port=system.membus.slave[2] +icache_port=system.membus.slave[1] + +[system.cpu.dtb] +type=SparcTLB +eventq_index=0 +size=64 + +[system.cpu.interrupts] +type=SparcInterrupts +eventq_index=0 + +[system.cpu.isa] +type=SparcISA +eventq_index=0 + +[system.cpu.itb] +type=SparcTLB +eventq_index=0 +size=64 + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=mcf mcf.in +cwd=build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-atomic +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/sparc/linux/mcf +gid=100 +input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=55300000000 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.membus] +type=CoherentXBar +clk_domain=system.clk_domain +eventq_index=0 +header_cycles=1 +snoop_filter=Null +system=system +use_default_range=false +width=8 +master=system.physmem.port +slave=system.system_port system.cpu.icache_port system.cpu.dcache_port + +[system.physmem] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=true +eventq_index=0 +in_addr_map=true +latency=30000 +latency_var=0 +null=false +range=0:268435455 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/mcf.out b/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/mcf.out new file mode 100644 index 000000000..095132477 --- /dev/null +++ b/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/mcf.out @@ -0,0 +1,999 @@ +() +500 +() +499 +() +498 +() +496 +() +495 +() +494 +() +493 +() +492 +() +491 +() +490 +() +489 +() +488 +() +487 +() +486 +() +484 +() +482 +() +481 +() +480 +() +479 +() +478 +() +477 +() +476 +() +475 +() +474 +() +473 +() +472 +() +471 +() +469 +() +468 +() +467 +() +466 +() +465 +() +464 +() +463 +() +462 +() +461 +() +460 +() +459 +() +458 +() +457 +() +455 +() +454 +() +452 +() +451 +() +450 +() +449 +() +448 +() +446 +() +445 +() +444 +() +443 +() +442 +() +440 +() +439 +() +438 +() +436 +() +435 +() +433 +() +432 +() +431 +() +428 +() +427 +() +425 +() +424 +() +423 +() +420 +() +419 +() +416 +() +414 +() +413 +() +412 +() +407 +() +406 +() +405 +() +404 +() +403 +() +402 +() +401 +() +400 +() +399 +() +398 +() +396 +() +395 +() +393 +() +392 +() +390 +() +389 +() +388 +() +387 +() +386 +() +385 +() +384 +() +383 +() +382 +() +381 +() +380 +() +379 +() +377 +() +375 +() +374 +() +373 +() +372 +() +371 +() +370 +() +369 +() +368 +() +366 +() +365 +() +364 +() +362 +() +361 +() +360 +() +359 +() +358 +() +357 +() +356 +() +355 +() +354 +() +352 +() +350 +() +347 +() +344 +() +342 +() +341 +() +340 +() +339 +() +338 +() +332 +() +325 +() +320 +*** +345 +() +319 +*** +497 +() +318 +*** +349 +() +317 +*** +408 +() +316 +*** +324 +() +315 +*** +328 +() +314 +*** +335 +() +313 +*** +378 +() +312 +*** +426 +() +311 +*** +411 +() +304 +*** +343 +() +303 +*** +417 +() +302 +*** +485 +() +301 +*** +363 +() +300 +*** +376 +() +299 +*** +333 +() +292 +*** +337 +() +291 +*** +409 +() +290 +*** +421 +() +289 +*** +437 +() +288 +*** +430 +() +287 +*** +348 +() +286 +*** +326 +() +284 +() +282 +*** +308 +() +279 +*** +297 +*** +305 +() +278 +() +277 +*** +307 +() +276 +*** +296 +() +273 +() +271 +() +265 +() +246 +*** +267 +() +245 +*** +280 +() +244 +*** +391 +() +243 +*** +330 +() +242 +*** +456 +() +241 +*** +346 +() +240 +*** +483 +() +239 +*** +260 +() +238 +*** +261 +() +237 +*** +262 +*** +294 +() +236 +*** +253 +() +229 +*** +397 +() +228 +*** +298 +() +227 +*** +415 +() +226 +*** +264 +() +224 +*** +232 +() +222 +*** +233 +() +217 +*** +250 +() +211 +*** +331 +() +210 +*** +394 +() +209 +*** +410 +() +208 +*** +321 +() +207 +*** +327 +() +206 +*** +309 +() +199 +*** +259 +() +198 +*** +219 +() +197 +*** +220 +() +195 +*** +429 +() +194 +*** +470 +() +193 +*** +274 +() +191 +*** +203 +() +190 +*** +263 +() +189 +215 +*** +230 +() +188 +*** +266 +*** +295 +() +182 +*** +329 +() +181 +*** +351 +() +180 +*** +441 +() +179 +*** +453 +() +178 +*** +418 +() +177 +*** +353 +() +176 +*** +422 +() +175 +*** +225 +*** +255 +() +174 +*** +269 +() +173 +*** +214 +() +172 +*** +186 +() +171 +*** +447 +() +170 +*** +270 +*** +306 +() +169 +*** +336 +() +168 +*** +285 +() +165 +*** +249 +() +146 +*** +154 +() +143 +*** +334 +() +142 +*** +216 +*** +257 +() +141 +*** +167 +*** +251 +() +140 +*** +162 +*** +293 +() +139 +*** +158 +() +137 +*** +166 +*** +201 +() +136 +*** +160 +() +134 +*** +221 +() +132 +*** +213 +() +131 +*** +187 +() +129 +*** +235 +() +128 +*** +153 +() +127 +*** +156 +() +126 +*** +159 +*** +218 +() +125 +*** +155 +() +124 +*** +157 +() +123 +*** +152 +() +116 +*** +135 +*** +163 +() +115 +*** +133 +*** +204 +*** +248 +() +114 +*** +192 +*** +212 +() +113 +*** +268 +() +112 +*** +367 +() +111 +*** +272 +() +110 +*** +434 +() +109 +*** +323 +() +108 +*** +281 +() +107 +*** +144 +*** +148 +() +106 +*** +275 +() +105 +*** +196 +*** +254 +() +104 +*** +138 +*** +161 +() +103 +*** +310 +() +102 +*** +223 +*** +252 +() +80 +() +70 +() +69 +() +68 +() +66 +() +64 +() +62 +*** +256 +() +61 +*** +93 +() +59 +*** +120 +() +58 +() +57 +*** +183 +() +55 +() +54 +() +52 +*** +147 +() +51 +*** +118 +() +50 +*** +83 +() +49 +*** +98 +() +48 +*** +99 +() +47 +() +46 +*** +184 +() +45 +*** +121 +() +44 +() +43 +*** +88 +() +42 +*** +122 +() +41 +*** +91 +() +40 +*** +96 +() +38 +*** +100 +() +37 +*** +149 +() +36 +*** +74 +() +35 +*** +258 +() +34 +*** +151 +() +33 +*** +85 +() +32 +() +31 +*** +94 +() +30 +*** +97 +() +29 +*** +90 +() +28 +*** +89 +() +27 +*** +92 +() +26 +*** +72 +*** +247 +() +25 +*** +86 +() +24 +*** +82 +() +23 +*** +87 +*** +117 +() +22 +*** +76 +*** +119 +() +21 +*** +84 +() +20 +*** +78 +() +19 +*** +73 +() +18 +*** +81 +() +17 +*** +65 +() +16 +*** +63 +*** +101 +() +15 +*** +71 +() +14 +*** +75 +() +13 +*** +322 +() +12 +*** +77 +() +11 +*** +283 +() +10 +*** +79 +() +9 +*** +145 +*** +150 +() +8 +*** +67 +() +7 +*** +60 +*** +231 +() +6 +*** +56 +*** +234 +() +5 +*** +164 +*** +202 +() +4 +*** +53 +() +3 +*** +130 +*** +185 +*** +200 +() +2 +*** +205 +() +1 +*** +39 +*** +95 diff --git a/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/simerr b/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/simerr new file mode 100755 index 000000000..1a4f96712 --- /dev/null +++ b/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/simerr @@ -0,0 +1 @@ +warn: Sockets disabled, not accepting gdb connections diff --git a/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/simout b/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/simout new file mode 100755 index 000000000..a8897be0c --- /dev/null +++ b/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/simout @@ -0,0 +1,26 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Jan 22 2014 17:04:27 +gem5 started Jan 22 2014 19:41:52 +gem5 executing on u200540-lin +command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-atomic +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... + +MCF SPEC version 1.6.I +by Andreas Loebel +Copyright (c) 1998,1999 ZIB Berlin +All Rights Reserved. + +nodes : 500 +active arcs : 1905 +simplex iterations : 1502 +flow value : 4990014995 +new implicit arcs : 23867 +active arcs : 25772 +simplex iterations : 2663 +flow value : 3080014995 +checksum : 68389 +optimal +Exiting @ tick 122215823500 because target called exit() diff --git a/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt new file mode 100644 index 000000000..c1c851704 --- /dev/null +++ b/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt @@ -0,0 +1,124 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.122216 # Number of seconds simulated +sim_ticks 122215823500 # Number of ticks simulated +final_tick 122215823500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 2069444 # Simulator instruction rate (inst/s) +host_op_rate 2069529 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1037295392 # Simulator tick rate (ticks/s) +host_mem_usage 412436 # Number of bytes of host memory used +host_seconds 117.82 # Real time elapsed on the host +sim_insts 243825150 # Number of instructions simulated +sim_ops 243835265 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 977685992 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 328674008 # Number of bytes read from this memory +system.physmem.bytes_read::total 1306360000 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 977685992 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 977685992 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 91606089 # Number of bytes written to this memory +system.physmem.bytes_written::total 91606089 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 244421498 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 82220433 # Number of read requests responded to by this memory +system.physmem.num_reads::total 326641931 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 22901951 # Number of write requests responded to by this memory +system.physmem.num_writes::total 22901951 # Number of write requests responded to by this memory +system.physmem.num_other::cpu.data 3886 # Number of other requests responded to by this memory +system.physmem.num_other::total 3886 # Number of other requests responded to by this memory +system.physmem.bw_read::cpu.inst 7999667834 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2689291768 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 10688959601 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7999667834 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7999667834 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 749543606 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 749543606 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7999667834 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3438835373 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 11438503207 # Total bandwidth to/from this memory (bytes/s) +system.membus.trans_dist::ReadReq 326641931 # Transaction distribution +system.membus.trans_dist::ReadResp 326641931 # Transaction distribution +system.membus.trans_dist::WriteReq 22901951 # Transaction distribution +system.membus.trans_dist::WriteResp 22901951 # Transaction distribution +system.membus.trans_dist::SwapReq 3886 # Transaction distribution +system.membus.trans_dist::SwapResp 3886 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 488842996 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 210252540 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 699095536 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 977685992 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 420311185 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1397997177 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 349547768 # Request fanout histogram +system.membus.snoop_fanout::mean 0.699251 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.458584 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 105126270 30.07% 30.07% # Request fanout histogram +system.membus.snoop_fanout::1 244421498 69.93% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 349547768 # Request fanout histogram +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.workload.num_syscalls 443 # Number of system calls +system.cpu.numCycles 244431648 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 243825150 # Number of instructions committed +system.cpu.committedOps 243835265 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 194726494 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 11630 # Number of float alu accesses +system.cpu.num_func_calls 4252956 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 18619959 # number of instructions that are conditional controls +system.cpu.num_int_insts 194726494 # number of integer instructions +system.cpu.num_fp_insts 11630 # number of float instructions +system.cpu.num_int_register_reads 456818988 # number of times the integer registers were read +system.cpu.num_int_register_writes 215451554 # number of times the integer registers were written +system.cpu.num_fp_register_reads 23256 # number of times the floating registers were read +system.cpu.num_fp_register_writes 90 # number of times the floating registers were written +system.cpu.num_mem_refs 105711441 # number of memory refs +system.cpu.num_load_insts 82803521 # Number of load instructions +system.cpu.num_store_insts 22907920 # Number of store instructions +system.cpu.num_idle_cycles 0.002000 # Number of idle cycles +system.cpu.num_busy_cycles 244431647.998000 # Number of busy cycles +system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.000000 # Percentage of idle cycles +system.cpu.Branches 29302884 # Number of branches fetched +system.cpu.op_class::No_OpClass 28877736 11.81% 11.81% # Class of executed instruction +system.cpu.op_class::IntAlu 109842388 44.94% 56.75% # Class of executed instruction +system.cpu.op_class::IntMult 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::FloatAdd 42 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::MemRead 82803527 33.88% 90.63% # Class of executed instruction +system.cpu.op_class::MemWrite 22907920 9.37% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 244431613 # Class of executed instruction + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/config.ini b/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/config.ini new file mode 100644 index 000000000..519142696 --- /dev/null +++ b/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/config.ini @@ -0,0 +1,207 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +eventq_index=0 +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=atomic +mem_ranges= +memories=system.physmem +num_work_ids=16 +readfile= +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=AtomicSimpleCPU +children=apic_clk_domain dtb interrupts isa itb tracer workload +branchPred=Null +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fastmem=false +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +profile=0 +progress_interval=0 +simpoint_start_insts= +simulate_data_stalls=false +simulate_inst_stalls=false +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +width=1 +workload=system.cpu.workload +dcache_port=system.membus.slave[2] +icache_port=system.membus.slave[1] + +[system.cpu.apic_clk_domain] +type=DerivedClockDomain +clk_divider=16 +clk_domain=system.cpu_clk_domain +eventq_index=0 + +[system.cpu.dtb] +type=X86TLB +children=walker +eventq_index=0 +size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=X86PagetableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +num_squash_per_cycle=4 +system=system +port=system.membus.slave[4] + +[system.cpu.interrupts] +type=X86LocalApic +clk_domain=system.cpu.apic_clk_domain +eventq_index=0 +int_latency=1000 +pio_addr=2305843009213693952 +pio_latency=100000 +system=system +int_master=system.membus.slave[5] +int_slave=system.membus.master[2] +pio=system.membus.master[1] + +[system.cpu.isa] +type=X86ISA +eventq_index=0 + +[system.cpu.itb] +type=X86TLB +children=walker +eventq_index=0 +size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=X86PagetableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +num_squash_per_cycle=4 +system=system +port=system.membus.slave[3] + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=mcf mcf.in +cwd=build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/mcf +gid=100 +input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=55300000000 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.membus] +type=CoherentXBar +clk_domain=system.clk_domain +eventq_index=0 +header_cycles=1 +snoop_filter=Null +system=system +use_default_range=false +width=8 +master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave +slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.int_master + +[system.physmem] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=true +eventq_index=0 +in_addr_map=true +latency=30000 +latency_var=0 +null=false +range=0:268435455 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/mcf.out b/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/mcf.out new file mode 100644 index 000000000..095132477 --- /dev/null +++ b/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/mcf.out @@ -0,0 +1,999 @@ +() +500 +() +499 +() +498 +() +496 +() +495 +() +494 +() +493 +() +492 +() +491 +() +490 +() +489 +() +488 +() +487 +() +486 +() +484 +() +482 +() +481 +() +480 +() +479 +() +478 +() +477 +() +476 +() +475 +() +474 +() +473 +() +472 +() +471 +() +469 +() +468 +() +467 +() +466 +() +465 +() +464 +() +463 +() +462 +() +461 +() +460 +() +459 +() +458 +() +457 +() +455 +() +454 +() +452 +() +451 +() +450 +() +449 +() +448 +() +446 +() +445 +() +444 +() +443 +() +442 +() +440 +() +439 +() +438 +() +436 +() +435 +() +433 +() +432 +() +431 +() +428 +() +427 +() +425 +() +424 +() +423 +() +420 +() +419 +() +416 +() +414 +() +413 +() +412 +() +407 +() +406 +() +405 +() +404 +() +403 +() +402 +() +401 +() +400 +() +399 +() +398 +() +396 +() +395 +() +393 +() +392 +() +390 +() +389 +() +388 +() +387 +() +386 +() +385 +() +384 +() +383 +() +382 +() +381 +() +380 +() +379 +() +377 +() +375 +() +374 +() +373 +() +372 +() +371 +() +370 +() +369 +() +368 +() +366 +() +365 +() +364 +() +362 +() +361 +() +360 +() +359 +() +358 +() +357 +() +356 +() +355 +() +354 +() +352 +() +350 +() +347 +() +344 +() +342 +() +341 +() +340 +() +339 +() +338 +() +332 +() +325 +() +320 +*** +345 +() +319 +*** +497 +() +318 +*** +349 +() +317 +*** +408 +() +316 +*** +324 +() +315 +*** +328 +() +314 +*** +335 +() +313 +*** +378 +() +312 +*** +426 +() +311 +*** +411 +() +304 +*** +343 +() +303 +*** +417 +() +302 +*** +485 +() +301 +*** +363 +() +300 +*** +376 +() +299 +*** +333 +() +292 +*** +337 +() +291 +*** +409 +() +290 +*** +421 +() +289 +*** +437 +() +288 +*** +430 +() +287 +*** +348 +() +286 +*** +326 +() +284 +() +282 +*** +308 +() +279 +*** +297 +*** +305 +() +278 +() +277 +*** +307 +() +276 +*** +296 +() +273 +() +271 +() +265 +() +246 +*** +267 +() +245 +*** +280 +() +244 +*** +391 +() +243 +*** +330 +() +242 +*** +456 +() +241 +*** +346 +() +240 +*** +483 +() +239 +*** +260 +() +238 +*** +261 +() +237 +*** +262 +*** +294 +() +236 +*** +253 +() +229 +*** +397 +() +228 +*** +298 +() +227 +*** +415 +() +226 +*** +264 +() +224 +*** +232 +() +222 +*** +233 +() +217 +*** +250 +() +211 +*** +331 +() +210 +*** +394 +() +209 +*** +410 +() +208 +*** +321 +() +207 +*** +327 +() +206 +*** +309 +() +199 +*** +259 +() +198 +*** +219 +() +197 +*** +220 +() +195 +*** +429 +() +194 +*** +470 +() +193 +*** +274 +() +191 +*** +203 +() +190 +*** +263 +() +189 +215 +*** +230 +() +188 +*** +266 +*** +295 +() +182 +*** +329 +() +181 +*** +351 +() +180 +*** +441 +() +179 +*** +453 +() +178 +*** +418 +() +177 +*** +353 +() +176 +*** +422 +() +175 +*** +225 +*** +255 +() +174 +*** +269 +() +173 +*** +214 +() +172 +*** +186 +() +171 +*** +447 +() +170 +*** +270 +*** +306 +() +169 +*** +336 +() +168 +*** +285 +() +165 +*** +249 +() +146 +*** +154 +() +143 +*** +334 +() +142 +*** +216 +*** +257 +() +141 +*** +167 +*** +251 +() +140 +*** +162 +*** +293 +() +139 +*** +158 +() +137 +*** +166 +*** +201 +() +136 +*** +160 +() +134 +*** +221 +() +132 +*** +213 +() +131 +*** +187 +() +129 +*** +235 +() +128 +*** +153 +() +127 +*** +156 +() +126 +*** +159 +*** +218 +() +125 +*** +155 +() +124 +*** +157 +() +123 +*** +152 +() +116 +*** +135 +*** +163 +() +115 +*** +133 +*** +204 +*** +248 +() +114 +*** +192 +*** +212 +() +113 +*** +268 +() +112 +*** +367 +() +111 +*** +272 +() +110 +*** +434 +() +109 +*** +323 +() +108 +*** +281 +() +107 +*** +144 +*** +148 +() +106 +*** +275 +() +105 +*** +196 +*** +254 +() +104 +*** +138 +*** +161 +() +103 +*** +310 +() +102 +*** +223 +*** +252 +() +80 +() +70 +() +69 +() +68 +() +66 +() +64 +() +62 +*** +256 +() +61 +*** +93 +() +59 +*** +120 +() +58 +() +57 +*** +183 +() +55 +() +54 +() +52 +*** +147 +() +51 +*** +118 +() +50 +*** +83 +() +49 +*** +98 +() +48 +*** +99 +() +47 +() +46 +*** +184 +() +45 +*** +121 +() +44 +() +43 +*** +88 +() +42 +*** +122 +() +41 +*** +91 +() +40 +*** +96 +() +38 +*** +100 +() +37 +*** +149 +() +36 +*** +74 +() +35 +*** +258 +() +34 +*** +151 +() +33 +*** +85 +() +32 +() +31 +*** +94 +() +30 +*** +97 +() +29 +*** +90 +() +28 +*** +89 +() +27 +*** +92 +() +26 +*** +72 +*** +247 +() +25 +*** +86 +() +24 +*** +82 +() +23 +*** +87 +*** +117 +() +22 +*** +76 +*** +119 +() +21 +*** +84 +() +20 +*** +78 +() +19 +*** +73 +() +18 +*** +81 +() +17 +*** +65 +() +16 +*** +63 +*** +101 +() +15 +*** +71 +() +14 +*** +75 +() +13 +*** +322 +() +12 +*** +77 +() +11 +*** +283 +() +10 +*** +79 +() +9 +*** +145 +*** +150 +() +8 +*** +67 +() +7 +*** +60 +*** +231 +() +6 +*** +56 +*** +234 +() +5 +*** +164 +*** +202 +() +4 +*** +53 +() +3 +*** +130 +*** +185 +*** +200 +() +2 +*** +205 +() +1 +*** +39 +*** +95 diff --git a/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/simerr b/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/simerr new file mode 100755 index 000000000..1a4f96712 --- /dev/null +++ b/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/simerr @@ -0,0 +1 @@ +warn: Sockets disabled, not accepting gdb connections diff --git a/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/simout b/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/simout new file mode 100755 index 000000000..ea41249d4 --- /dev/null +++ b/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/simout @@ -0,0 +1,26 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Jan 22 2014 17:10:34 +gem5 started Jan 22 2014 20:16:46 +gem5 executing on u200540-lin +command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... + +MCF SPEC version 1.6.I +by Andreas Loebel +Copyright (c) 1998,1999 ZIB Berlin +All Rights Reserved. + +nodes : 500 +active arcs : 1905 +simplex iterations : 1502 +flow value : 4990014995 +new implicit arcs : 23867 +active arcs : 25772 +simplex iterations : 2663 +flow value : 3080014995 +checksum : 68389 +optimal +Exiting @ tick 168950040000 because target called exit() diff --git a/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt new file mode 100644 index 000000000..844bb352a --- /dev/null +++ b/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt @@ -0,0 +1,129 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.168950 # Number of seconds simulated +sim_ticks 168950040000 # Number of ticks simulated +final_tick 168950040000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 1180838 # Simulator instruction rate (inst/s) +host_op_rate 2079266 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1262766288 # Simulator tick rate (ticks/s) +host_mem_usage 436624 # Number of bytes of host memory used +host_seconds 133.79 # Real time elapsed on the host +sim_insts 157988548 # Number of instructions simulated +sim_ops 278192465 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 1741569312 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 717246013 # Number of bytes read from this memory +system.physmem.bytes_read::total 2458815325 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1741569312 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1741569312 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 243173117 # Number of bytes written to this memory +system.physmem.bytes_written::total 243173117 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 217696164 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 90779447 # Number of read requests responded to by this memory +system.physmem.num_reads::total 308475611 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 31439752 # Number of write requests responded to by this memory +system.physmem.num_writes::total 31439752 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 10308191179 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 4245314254 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14553505433 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 10308191179 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 10308191179 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1439319677 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1439319677 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 10308191179 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5684633931 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 15992825110 # Total bandwidth to/from this memory (bytes/s) +system.membus.trans_dist::ReadReq 308475611 # Transaction distribution +system.membus.trans_dist::ReadResp 308475611 # Transaction distribution +system.membus.trans_dist::WriteReq 31439752 # Transaction distribution +system.membus.trans_dist::WriteResp 31439752 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 435392328 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.icache_port::total 435392328 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 244438398 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::total 244438398 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 679830726 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1741569312 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::total 1741569312 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 960419130 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::total 960419130 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 2701988442 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 339915363 # Request fanout histogram +system.membus.snoop_fanout::mean 2.640442 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.479871 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::2 122219199 35.96% 35.96% # Request fanout histogram +system.membus.snoop_fanout::3 217696164 64.04% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 2 # Request fanout histogram +system.membus.snoop_fanout::max_value 3 # Request fanout histogram +system.membus.snoop_fanout::total 339915363 # Request fanout histogram +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks +system.cpu.workload.num_syscalls 444 # Number of system calls +system.cpu.numCycles 337900081 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 157988548 # Number of instructions committed +system.cpu.committedOps 278192465 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 278169482 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses +system.cpu.num_func_calls 8475189 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 18628007 # number of instructions that are conditional controls +system.cpu.num_int_insts 278169482 # number of integer instructions +system.cpu.num_fp_insts 40 # number of float instructions +system.cpu.num_int_register_reads 635379407 # number of times the integer registers were read +system.cpu.num_int_register_writes 217447860 # number of times the integer registers were written +system.cpu.num_fp_register_reads 40 # number of times the floating registers were read +system.cpu.num_fp_register_writes 26 # number of times the floating registers were written +system.cpu.num_cc_register_reads 104140596 # number of times the CC registers were read +system.cpu.num_cc_register_writes 61764861 # number of times the CC registers were written +system.cpu.num_mem_refs 122219137 # number of memory refs +system.cpu.num_load_insts 90779385 # Number of load instructions +system.cpu.num_store_insts 31439752 # Number of store instructions +system.cpu.num_idle_cycles 0.002000 # Number of idle cycles +system.cpu.num_busy_cycles 337900080.998000 # Number of busy cycles +system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.000000 # Percentage of idle cycles +system.cpu.Branches 29309705 # Number of branches fetched +system.cpu.op_class::No_OpClass 16695 0.01% 0.01% # Class of executed instruction +system.cpu.op_class::IntAlu 155945354 56.06% 56.06% # Class of executed instruction +system.cpu.op_class::IntMult 10938 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::IntDiv 329 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::FloatAdd 12 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::MemRead 90779385 32.63% 88.70% # Class of executed instruction +system.cpu.op_class::MemWrite 31439752 11.30% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 278192465 # Class of executed instruction + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/10.mcf/test.py b/tests/quick/se/10.mcf/test.py new file mode 100644 index 000000000..0ea3f370d --- /dev/null +++ b/tests/quick/se/10.mcf/test.py @@ -0,0 +1,34 @@ +# Copyright (c) 2006-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Korey Sewell + +m5.util.addToPath('../configs/common') +from cpu2000 import mcf + +workload = mcf(isa, opsys, 'smred') +root.system.cpu[0].workload = workload.makeLiveProcess() +root.system.physmem.range=AddrRange('256MB') diff --git a/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini b/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini new file mode 100644 index 000000000..44bc5cf02 --- /dev/null +++ b/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini @@ -0,0 +1,172 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +eventq_index=0 +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=atomic +mem_ranges= +memories=system.physmem +num_work_ids=16 +readfile= +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=AtomicSimpleCPU +children=dtb interrupts isa itb tracer workload +branchPred=Null +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fastmem=false +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +profile=0 +progress_interval=0 +simpoint_start_insts= +simulate_data_stalls=false +simulate_inst_stalls=false +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +width=1 +workload=system.cpu.workload +dcache_port=system.membus.slave[2] +icache_port=system.membus.slave[1] + +[system.cpu.dtb] +type=AlphaTLB +eventq_index=0 +size=64 + +[system.cpu.interrupts] +type=AlphaInterrupts +eventq_index=0 + +[system.cpu.isa] +type=AlphaISA +eventq_index=0 +system=system + +[system.cpu.itb] +type=AlphaTLB +eventq_index=0 +size=48 + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook +cwd=build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-atomic +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/eon +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.membus] +type=CoherentXBar +clk_domain=system.clk_domain +eventq_index=0 +header_cycles=1 +snoop_filter=Null +system=system +use_default_range=false +width=8 +master=system.physmem.port +slave=system.system_port system.cpu.icache_port system.cpu.dcache_port + +[system.physmem] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=true +eventq_index=0 +in_addr_map=true +latency=30000 +latency_var=0 +null=false +range=0:134217727 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/simerr b/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/simerr new file mode 100755 index 000000000..664365742 --- /dev/null +++ b/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/simerr @@ -0,0 +1,51 @@ +warn: Sockets disabled, not accepting gdb connections +warn: Prefetch instructions in Alpha do not do anything +warn: Prefetch instructions in Alpha do not do anything +warn: Prefetch instructions in Alpha do not do anything +getting pixel output filename pixels_out.cook +opening control file chair.control.cook +opening camera file chair.camera +opening surfaces file chair.surfaces +reading data +processing 8parts +Grid measure is 6 by 3.0001 by 6 +cell dimension is 0.863065 +Creating grid for list of length 21 +Grid size = 7 by 4 by 7 +Total occupancy = 236 +reading control stream +reading camera stream +Writing to chair.cook.ppm +calculating 15 by 15 image with 196 samples +col 0. . . +col 1. . . +col 2. . . +col 3. . . +col 4. . . +col 5. . . +col 6. . . +col 7. . . +col 8. . . +col 9. . . +col 10. . . +col 11. . . +col 12. . . +col 13. . . +col 14. . . +Writing to chair.cook.ppm +0 8 14 +1 8 14 +2 8 14 +3 8 14 +4 8 14 +5 8 14 +6 8 14 +7 8 14 +8 8 14 +9 8 14 +10 8 14 +11 8 14 +12 8 14 +13 8 14 +14 8 14 +warn: ignoring syscall sigprocmask(1, ...) diff --git a/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/simout b/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/simout new file mode 100755 index 000000000..e4df23735 --- /dev/null +++ b/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/simout @@ -0,0 +1,14 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Jan 22 2014 16:27:55 +gem5 started Jan 22 2014 17:48:27 +gem5 executing on u200540-lin +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-atomic +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +Eon, Version 1.1 +info: Increasing stack size by one page. +OO-style eon Time= 0.183333 +Exiting @ tick 199332411500 because target called exit() diff --git a/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt b/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt new file mode 100644 index 000000000..7803b8dd6 --- /dev/null +++ b/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt @@ -0,0 +1,152 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.199332 # Number of seconds simulated +sim_ticks 199332411500 # Number of ticks simulated +final_tick 199332411500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 2820224 # Simulator instruction rate (inst/s) +host_op_rate 2820224 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1410112599 # Simulator tick rate (ticks/s) +host_mem_usage 285836 # Number of bytes of host memory used +host_seconds 141.36 # Real time elapsed on the host +sim_insts 398664595 # Number of instructions simulated +sim_ops 398664595 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 1594658604 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 662449271 # Number of bytes read from this memory +system.physmem.bytes_read::total 2257107875 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1594658604 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1594658604 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 492356798 # Number of bytes written to this memory +system.physmem.bytes_written::total 492356798 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 398664651 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 94754489 # Number of read requests responded to by this memory +system.physmem.num_reads::total 493419140 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 73520729 # Number of write requests responded to by this memory +system.physmem.num_writes::total 73520729 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 7999996548 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3323339471 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 11323336020 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7999996548 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7999996548 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 2470028804 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2470028804 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7999996548 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5793368275 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 13793364824 # Total bandwidth to/from this memory (bytes/s) +system.membus.trans_dist::ReadReq 493419140 # Transaction distribution +system.membus.trans_dist::ReadResp 493419140 # Transaction distribution +system.membus.trans_dist::WriteReq 73520729 # Transaction distribution +system.membus.trans_dist::WriteResp 73520729 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 797329302 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 336550436 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1133879738 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1594658604 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 1154806069 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 2749464673 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 566939869 # Request fanout histogram +system.membus.snoop_fanout::mean 0.703187 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.456853 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 168275218 29.68% 29.68% # Request fanout histogram +system.membus.snoop_fanout::1 398664651 70.32% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 566939869 # Request fanout histogram +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.read_hits 94754489 # DTB read hits +system.cpu.dtb.read_misses 21 # DTB read misses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 94754510 # DTB read accesses +system.cpu.dtb.write_hits 73520729 # DTB write hits +system.cpu.dtb.write_misses 35 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 73520764 # DTB write accesses +system.cpu.dtb.data_hits 168275218 # DTB hits +system.cpu.dtb.data_misses 56 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 168275274 # DTB accesses +system.cpu.itb.fetch_hits 398664651 # ITB hits +system.cpu.itb.fetch_misses 173 # ITB misses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 398664824 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 215 # Number of system calls +system.cpu.numCycles 398664824 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 398664595 # Number of instructions committed +system.cpu.committedOps 398664595 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 316365907 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 155295119 # Number of float alu accesses +system.cpu.num_func_calls 16015498 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 25997787 # number of instructions that are conditional controls +system.cpu.num_int_insts 316365907 # number of integer instructions +system.cpu.num_fp_insts 155295119 # number of float instructions +system.cpu.num_int_register_reads 372938760 # number of times the integer registers were read +system.cpu.num_int_register_writes 159335860 # number of times the integer registers were written +system.cpu.num_fp_register_reads 151776196 # number of times the floating registers were read +system.cpu.num_fp_register_writes 100196481 # number of times the floating registers were written +system.cpu.num_mem_refs 168275274 # number of memory refs +system.cpu.num_load_insts 94754510 # Number of load instructions +system.cpu.num_store_insts 73520764 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 398664824 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 44587532 # Number of branches fetched +system.cpu.op_class::No_OpClass 23123356 5.80% 5.80% # Class of executed instruction +system.cpu.op_class::IntAlu 141652555 35.53% 41.33% # Class of executed instruction +system.cpu.op_class::IntMult 2124322 0.53% 41.86% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 41.86% # Class of executed instruction +system.cpu.op_class::FloatAdd 35620060 8.93% 50.80% # Class of executed instruction +system.cpu.op_class::FloatCmp 7072549 1.77% 52.57% # Class of executed instruction +system.cpu.op_class::FloatCvt 2735231 0.69% 53.26% # Class of executed instruction +system.cpu.op_class::FloatMult 16498021 4.14% 57.40% # Class of executed instruction +system.cpu.op_class::FloatDiv 1563283 0.39% 57.79% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 57.79% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 57.79% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 57.79% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 57.79% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 57.79% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 57.79% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 57.79% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 57.79% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 57.79% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 57.79% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 57.79% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 57.79% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 57.79% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 57.79% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 57.79% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 57.79% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 57.79% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 57.79% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 57.79% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 57.79% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 57.79% # Class of executed instruction +system.cpu.op_class::MemRead 94754510 23.77% 81.56% # Class of executed instruction +system.cpu.op_class::MemWrite 73520764 18.44% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 398664651 # Class of executed instruction + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/30.eon/test.py b/tests/quick/se/30.eon/test.py new file mode 100644 index 000000000..2ad1ef429 --- /dev/null +++ b/tests/quick/se/30.eon/test.py @@ -0,0 +1,33 @@ +# Copyright (c) 2006-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Korey Sewell + +m5.util.addToPath('../configs/common') +from cpu2000 import eon_cook + +workload = eon_cook(isa, opsys, 'mdred') +root.system.cpu[0].workload = workload.makeLiveProcess()