From: lkcl <lkcl@web>
Date: Sun, 3 Jul 2022 19:23:39 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~1376
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ed117a1cbccf10e581727ce1bdba1d3ad3495d51;p=libreriscv.git

---

diff --git a/openpower/sv/setvl.mdwn b/openpower/sv/setvl.mdwn
index d6cb15dc0..dcbfec2e5 100644
--- a/openpower/sv/setvl.mdwn
+++ b/openpower/sv/setvl.mdwn
@@ -96,12 +96,16 @@ Note that the immediate (`SVi`) spans 7 bits (16 to 22)
 * `vf` - bit 25 - sets "Vertical First Mode".
 
 Note that in immediate setting mode VL and MVL start from **one**
-i.e. that an immediate value of zero will result in VL/MVL being set to 1.
-0b111111 results in VL/MVL being set to 64. This is because setting
+but that this is compensated for in the assembly notation.
+i.e. that an immediate value of 1 in assembler notation
+actually places the value 0b0000000 in the `SVi` field bits:
+on execution the `setvl` instruction adds one to the decoded
+`SVi` field bits, resulting in
+VL/MVL being set to 1. This is because setting
 VL/MVL to 1 results in "scalar identity" behaviour, where setting VL/MVL
 to 0 would result in all Vector operations becoming `nop`.  If this is
 truly desired (nop behaviour) then setting VL and MVL to zero is to be
-done via the [[SVSTATE SPR|sv/sprs]]
+done via the [[SVSTATE SPR|sv/sprs]].
 
 Note that setmvli is a pseudo-op, based on RA/RT=0, and setvli likewise