From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 9 Dec 2021 15:45:09 +0000 (+0000)
Subject: wire fetch_failed from I-Cache to PowerDecoder2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ed1504b692c40bed445a48fbb58fdde32dea4da6;p=soc.git

wire fetch_failed from I-Cache to PowerDecoder2
informs PowerDecoder2 that an instruction fetch failed in MMU mode
---

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index 055c4c00..6aa79019 100644
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -693,6 +693,13 @@ class TestIssuerInternal(Elaboratable):
         # note if an exception happened.  in a pipelined or OoO design
         # this needs to be accompanied by "shadowing" (or stalling)
         exc_happened = self.core.o.exc_happened
+        # also note instruction fetch failed
+        if hasattr(core, "icache"):
+            fetch_failed = core.icache.i_out.fetch_failed
+        else:
+            fetch_failed = Const(0, 1)
+        # set to zero initially
+        sync += pdecode2.instr_fault.eq(0)
 
         with m.FSM(name="issue_fsm"):
 
@@ -848,6 +855,9 @@ class TestIssuerInternal(Elaboratable):
                 # allowing it to be set again during the next execution
                 sync += pdecode2.ldst_exc.eq(0)
 
+                # update (highest priority) instruction fault
+                sync += pdecode2.instr_fault.eq(fetch_failed)
+
                 m.next = "INSN_EXECUTE"  # move to "execute"
 
             # handshake with execution FSM, move to "wait" once acknowledged