From: Samuel Pitoiset Date: Fri, 6 Apr 2018 14:00:08 +0000 (+0200) Subject: radv: clean up radv_vi_dcc_enabled() X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ed41e776d03d27d2874f9b02e00bbd1f2226528f;p=mesa.git radv: clean up radv_vi_dcc_enabled() And rename to radv_dcc_enabled() to be consistent. Signed-off-by: Samuel Pitoiset Reviewed-by: Bas Nieuwenhuizen --- diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c index caf6f00e634..846639eab0d 100644 --- a/src/amd/vulkan/radv_device.c +++ b/src/amd/vulkan/radv_device.c @@ -3560,7 +3560,7 @@ radv_initialise_color_surface(struct radv_device *device, !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS)) cb->cb_color_info |= S_028C70_FAST_CLEAR(1); - if (radv_vi_dcc_enabled(iview->image, iview->base_mip)) + if (radv_dcc_enabled(iview->image, iview->base_mip)) cb->cb_color_info |= S_028C70_DCC_ENABLE(1); if (device->physical_device->rad_info.chip_class >= VI) { diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c index 56b9ba1cdaf..1a8352fea27 100644 --- a/src/amd/vulkan/radv_image.c +++ b/src/amd/vulkan/radv_image.c @@ -294,7 +294,7 @@ si_set_mutable_tex_desc_fields(struct radv_device *device, if (chip_class >= VI) { state[6] &= C_008F28_COMPRESSION_EN; state[7] = 0; - if (!is_storage_image && radv_vi_dcc_enabled(image, first_level)) { + if (!is_storage_image && radv_dcc_enabled(image, first_level)) { meta_va = gpu_address + image->dcc_offset; if (chip_class <= VI) meta_va += base_level_info->dcc_offset; diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index f954d678740..97f4cf657d8 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -1384,12 +1384,6 @@ bool radv_layout_dcc_compressed(const struct radv_image *image, VkImageLayout layout, unsigned queue_mask); -static inline bool -radv_vi_dcc_enabled(const struct radv_image *image, unsigned level) -{ - return image->surface.dcc_size && level < image->surface.num_dcc_levels; -} - /** * Return whether the image has CMASK metadata for color surfaces. */ @@ -1417,6 +1411,16 @@ radv_image_has_dcc(const struct radv_image *image) return image->surface.dcc_size; } +/** + * Return whether DCC metadata is enabled for a level. + */ +static inline bool +radv_dcc_enabled(const struct radv_image *image, unsigned level) +{ + return radv_image_has_dcc(image) && + level < image->surface.num_dcc_levels; +} + /** * Return whether the image has HTILE metadata for depth surfaces. */