From: Robert Kovacsics <rmk35@cl.cam.ac.uk>
Date: Fri, 13 Jul 2018 13:21:53 +0000 (+0100)
Subject: mem-cache: Typo in comment: 'proceed' -> 'precede'
X-Git-Tag: v19.0.0.0~1999
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ed427a3fcdf49a0ea0afa212c96240a04d4678d7;p=gem5.git

mem-cache: Typo in comment: 'proceed' -> 'precede'

The writebacks happen before anything below, not after.

Change-Id: I7eaefbbf33aa17c496255dedd964a56118a28741
Reviewed-on: https://gem5-review.googlesource.com/11749
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
---

diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index 8fd9ac298..c1ebdd6c0 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -348,7 +348,7 @@ BaseCache::recvTimingReq(PacketPtr pkt)
         satisfied = access(pkt, blk, lat, writebacks);
 
         // copy writebacks to write buffer here to ensure they logically
-        // proceed anything happening below
+        // precede anything happening below
         doWritebacks(writebacks, forward_time);
     }
 
@@ -593,7 +593,7 @@ BaseCache::recvAtomic(PacketPtr pkt)
     }
 
     // handle writebacks resulting from the access here to ensure they
-    // logically proceed anything happening below
+    // logically precede anything happening below
     doWritebacksAtomic(writebacks);
     assert(writebacks.empty());