From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 13 Aug 2019 19:19:26 +0000 (-0700)
Subject: Add assign PCOUT = P to DSP48E1
X-Git-Tag: working-ls180~1039^2~241
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ed4b2834ef6ed811318c897bd6f8b19b6ec15f38;p=yosys.git

Add assign PCOUT = P to DSP48E1
---

diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 2731cb454..02ce0d61b 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -784,4 +784,6 @@ module DSP48E1 (
         end
     endgenerate
 
+    assign PCOUT = P;
+
 endmodule