From: Nanley Chery <nanley.g.chery@intel.com>
Date: Thu, 27 Apr 2017 23:22:03 +0000 (-0700)
Subject: anv/blorp: Move the depth cache flush outside of BLORP
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ed5801864ede0a04fb5fa80bf9ffea40e5c0e022;p=mesa.git

anv/blorp: Move the depth cache flush outside of BLORP

Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
---

diff --git a/src/intel/blorp/blorp_genX_exec.h b/src/intel/blorp/blorp_genX_exec.h
index a354cea117a..2276d7c06bb 100644
--- a/src/intel/blorp/blorp_genX_exec.h
+++ b/src/intel/blorp/blorp_genX_exec.h
@@ -1500,14 +1500,6 @@ blorp_emit_gen8_hiz_op(struct blorp_batch *batch,
    }
 
    blorp_emit(batch, GENX(3DSTATE_WM_HZ_OP), hzp);
-
-   /* Perform depth clear specific flushing */
-   if (params->hiz_op == BLORP_HIZ_OP_DEPTH_CLEAR && params->depth.enabled) {
-      blorp_emit(batch, GENX(PIPE_CONTROL), pc) {
-         pc.DepthStallEnable = true;
-         pc.DepthCacheFlushEnable = true;
-      }
-   }
 }
 #endif
 
diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c
index d94a2f89fa5..a869eebc241 100644
--- a/src/intel/vulkan/anv_blorp.c
+++ b/src/intel/vulkan/anv_blorp.c
@@ -1323,6 +1323,22 @@ anv_cmd_buffer_clear_subpass(struct anv_cmd_buffer *cmd_buffer)
                                              clear_depth, clear_stencil,
                                              clear_att.clearValue.
                                                 depthStencil.stencil);
+
+            /* From the SKL PRM, Depth Buffer Clear:
+             *
+             * Depth Buffer Clear Workaround
+             * Depth buffer clear pass using any of the methods (WM_STATE,
+             * 3DSTATE_WM or 3DSTATE_WM_HZ_OP) must be followed by a
+             * PIPE_CONTROL command with DEPTH_STALL bit and Depth FLUSH bits
+             * “set” before starting to render. DepthStall and DepthFlush are
+             * not needed between consecutive depth clear passes nor is it
+             * required if the depth-clear pass was done with “full_surf_clear”
+             * bit set in the 3DSTATE_WM_HZ_OP.
+             */
+            if (clear_depth) {
+               cmd_buffer->state.pending_pipe_bits |=
+                  ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | ANV_PIPE_DEPTH_STALL_BIT;
+            }
          }
       }