From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 9 Jul 2013 21:53:55 +0000 (+0200)
Subject: Fixed sign propagation in bit-wise operators
X-Git-Tag: yosys-0.2.0~538
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ed62fcdbe224207434c5f643734f2627264826c5;p=yosys.git

Fixed sign propagation in bit-wise operators
---

diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index 830778227..7a9c8ba64 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -896,6 +896,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 			int width = std::max(left.width, right.width);
 			if (width_hint > 0)
 				width = width_hint;
+			is_signed = children[0]->is_signed && children[1]->is_signed;
 			return binop2rtlil(this, type_name, width, left, right);
 		}